@@TheVertex-Engg-Lectures Mam last question ? Timing diagram for maximum mode .you upload two vedio one is english and another is hindi . in two different vedio diagram is different now i have a confusion which one is correct?
@@aminul_islam_rafi for maximum mode block diagram refer any, both are correct. For timing diagram refer seperate video on timing diagram/ bus cycle in Hindi
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BEST VIDEO I EVER FOUND THE COMPLETE PACKAGE
Thanks for your comment ☺️
Mam are these read/write diagrams ok to draw in exams as I have prepared them only
Yes
THANK YOU MA'AM
You are welcome 🤗 keep learning
mam yeh jo apne side m s0 s1 s2 likha h isme b pattern according change krna h? on timing 16:22 kyunki design to same hi rh rha h
Yes pattern changes. It is different for ioread write , memory read write etc. It is given in more detail in pin diagram video
@@TheVertex-Engg-Lectures ok thanku mam
@@TheVertex-Engg-Lectures Ma'am, Could you tell me why memory writes have a propagation delay?
@@word___addict8768 it's not delay, write goes low when data flows on ad0 to ad15
@@TheVertex-Engg-Lectures no ma'am not for write bar i m asking for ad0 to ad15
Mam we know that transreceiver is for data transfer .But during t1 cycle why you pass address to this ?
Without passing address we can not access data. Watch queue instruction working video for clear understanding
@@TheVertex-Engg-Lectures Mam is it like this ? First address pass. than it pass the data by transreceiver.
@@aminul_islam_rafi yes
@@TheVertex-Engg-Lectures Mam last question ?
Timing diagram for maximum mode .you upload two vedio one is english and another is hindi .
in two different vedio diagram is different now i have a confusion which one is correct?
@@aminul_islam_rafi for maximum mode block diagram refer any, both are correct. For timing diagram refer seperate video on timing diagram/ bus cycle in Hindi
Mam ek hi topic pr 2 vedio ku bnayi hai
In this bus cycle is explained in detail with animation