MOSFET Gate Capacitance Part 2

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  • Опубликовано: 2 окт 2024
  • / edmundsj
    If you want to see more of these videos, or would like to say thanks for this one, the best way you can do that is by becoming a patron - see the link above :). And a huge thank you to all my existing patrons - you make these videos possible.
    In this video, I continue my discussion of the MOSFET gate capacitance, and explain what happens when we apply a gate voltage larger than VT. The capacitance increases to a value of Cox, but it is now actually distributed between the gate and the source/drain terminals.
    This is part of my series on semiconductor physics (often called Electronics 1 at university). This is based on the book Semiconductor Physics and Devices by Donald Neamen, as well as the EECS 170A/174 courses taught at UC Irvine.
    Hope you found this video helpful, please post in the comments below anything I can do to improve future videos, or suggestions you have for future videos.

Комментарии • 15

  • @ly3282
    @ly3282 5 лет назад +4

    sir,I'm so confused,1.why Cgb=0 when there's a depletion region between inversion layer and bulk?in last video u said Cgb(when MOSFET is off)is equal to Cgate-dp in series with Cdp-bulk,so in this case Cgate-dp is 0 but Cdp-bulk is not,so shouldn't Cgs =Cdp-bulk?
    2.please correct me if I'm wrong,so in accumulation process,Cgb is equal to Cox*A which is a constant ,and this is Cin in your video,the capacitance decrease as u increase voltage ,so why is Cgb equal to 0 after inversion? shouldn't it equal to Cox*A?

  • @ravikiran.s.e.
    @ravikiran.s.e. 6 лет назад +4

    Sir,
    It's easy to understand and short. Thanks for the video.
    As a suggestion you could have explained MoS capacitances for different regions of operations such as cutoff, linear and Saturation.

    • @JordanEdmundsEECS
      @JordanEdmundsEECS  6 лет назад +3

      Yes, that’s actually a great idea, I will probably do that this/next weekend.

    • @arshaan256
      @arshaan256 4 года назад +1

      @@JordanEdmundsEECS Sir, when are you planning to release the video on the aforementioned topics?

    • @손동진-c5p
      @손동진-c5p 4 года назад

      언제 올리세요?

  • @oksky58
    @oksky58 5 лет назад +1

    I luv all of your lecture Sir! Thank u so much, But Why is that Cgb = 0? isn't it g-side is positive and b-side is negative?

  • @avianmotors
    @avianmotors 4 года назад +1

    If I want to use a device as a capacitor, would I be better off inverting the channel by gate-to-N+ capacitor, or enhancing the channel by gate-to-P+. It would seem to me that starting with a channel already enhanced (change the N+ to P+) would yield a better capacitor. Yet some of my coworkers think not. Am I missing something?

    • @jordanedmunds4460
      @jordanedmunds4460 4 года назад

      This is an extremely subtle question I only recently encountered myself. At first glance, it shouldn't matter. The capacitance will be the same either way since you have a sea of carriers separated by the gate oxide (regardless of their identity). However, if those carriers are electrons and your substrate it p-type (the channel is inverted), then those electrons are minority carriers. And when you need to charge and discharge your capacitor, it just takes more time to wait for the electrons to get generated by the substrate (this is how we actually get the electrons for inverting the channel in the first place). In contrast, if we use holes from a p-type substrate (put the capacitor in accumulation mode), we can inject those holes from nearby contacts and get them easily from the substrate (which has an excess of holes). See Neamen Sec 10.2 on C/V characteristics of MOS structures.

  • @TheMuhendistv
    @TheMuhendistv 4 года назад

    Why is Cgb = 0 when electrons do not move freely? Can you explain please? Or which video is the explanation for this situation?

  • @theamazingagares9043
    @theamazingagares9043 2 года назад

    hello sir first i want to thank you for this excellent set of videos ,but i have a question about Cgb=0 you said it is because of the électrique Field kepping the electrons from moving but it is thanks to the électrique Field that we have charge accumulation on each kind of capacitance so if i follow this, each electrique field is keeping the charges it attracts from moving thaen all capacitance would be =0 if it is like this
    am i messing some thing ?

  • @carlosfuentes475
    @carlosfuentes475 4 года назад +2

    Hello! Big fan over here! You really have an awesome teaching style :). I just wanted to ask you a question though. In minute 4:17 you mentioned that the minimum capacitance happens at a certain unknown voltage. And to calculate it, we need to use the condition for when the depletion region is at its max: phi(si) = 2phi(fp). But this is the condition for inversion, and therefore the condition for which the threshold voltage was calculated. Shouldn't it then have to be the threshold voltage the one at which the capacitance is at its minimum? Thank you very much in advance!

  • @kairiemenschneider2634
    @kairiemenschneider2634 3 года назад

    fing hero

  • @yassineoubaid5321
    @yassineoubaid5321 2 года назад

    thanks