Combinational Logic Design-I

[@ayushgautam8000]

Awesome Lecture, all concepts cleared.

[@shubhamkumarsaurav5212]

Thanks a lot sir.....for providing such a great video series.

[@chelladhurais1995]

@19.09 though we are not going to connect nmos in pullup network.
If it happens, Why drain should be connected to output and source should be to vdd i think its wrong since current in nmos is from drain to source

[@pratikpawar5842]

I have a Question.
@ 41.18 Why we flip the PMOS created diagram. Can't we keep the same without fliping. N Why?
Can I get my answer?

[@D.s.bisht1009]

nand truth table wrong 33:00

[@dhruvandangar9972]

no its true look again .

[@Golukumar-vj6kk]

After some time it gets corrected.

[@YelletiVaralakshmi]

Very poor explanation...... Better refer other channels

[@msivakumar450]

Time waste

[@sohamroy7668]

Very poor explanation