Thank you, professor, for your speed of delivering points is good. You are clearing all doubts before arising in my mind. I want faculty like you for teaching VLSI. Again Thank You PROFESSOR
Sir it was fantastic lecture I have ever listen till. Too nice derailing has been done by your side. Actually I studied this subject 11 years before and then almost no connection..but your lecture reminds or revive everything to me very very clearly. Thanks
@@hvkeee Prof saheb is telling that Vt is controlled by Vbi ( junction built in potential) tells a lot about state of affair in IIT... may be reservation is cause
50:20 One side is specified as source and other as drain just because of the voltage difference .as we all know that the source is grounded the side which has lower potential is known as source and the side with higher potential is known as drain.
Answer to the question asked at 24:28 --The one which is connected to higher potential (Vdd) is drain and the one which is connected to lower potential (vss) is source . It is called symmetric because rise time and fall time are equal, device ratio is unity.
At 40:48, i think in depletion type n-MOSFET there is a physically implanted channel(as i have read from the books) . It does not have an N-type substrate as you quoted sir. But when there is a channel already present then how does the electric field modulate the channel which is the basic working of a MOSFET.
What is the most suitable answer for the question asked at 24:32? if mos structure is symmetrical then why one region is called source and another drain?
Because although they seem diagrammatically similar, at high frequency of operation, they do not exhibit the same capacitances (because they are made that way, they source being closer to the bulk). So yeah, sure for DC operation their switching action is symmetrical but not in computer circuits operating at GHz frequencies.
Very nice presentation sir , i really got some additional exposure than what i know already. Thank you so much sir , Have a great day sir. Srinivas , Hyderabad.
good discussion, most of the circuit analysis, we use the convention current was is based on "holes" so opposite of "electron". So, when we say S-to-D that is the "electron" current, in circuit analysis (textbooks), most of the time we are assuming the convention or "hole" current which so D-to-S current. It can be confusing.
Sir I am Vinay, from telangana .Sir I have registered for cmos vlsi designing as my nptel course .Sir I had a doubt that some will complete their course fastly and some by some delay then,exam date will be fixed or based on completion we can write the exam ?
In 51 minute video right .....you try to teach well right ....but i can't get you right ....please make this lecture in hindi right ....but only if your hindi is right ....sorry sir ...right...
Clearly explanated everything... I am glad i come to this channel finally... But my graduation is completed .
Thank you, professor, for your speed of delivering points is good. You are clearing all doubts before arising in my mind. I want faculty like you for teaching VLSI. Again Thank You PROFESSOR
Sir it was fantastic lecture I have ever listen till. Too nice derailing has been done by your side. Actually I studied this subject 11 years before and then almost no connection..but your lecture reminds or revive everything to me very very clearly. Thanks
This was a fabulous lecture. I must appreciate the faculty for his knowledge and very good delivery. Also, thank for clarifying many basic concepts.
Sir ur interest towards subject made me to see this lecture video full....
@@hvkeee Prof saheb is telling that Vt is controlled by Vbi ( junction built in potential) tells a lot about state of affair in IIT... may be reservation is cause
No wrong their@@VikramchauhanChauhan-pn5ol
Excellent explainations best teacher ever , thanks a lot sir this was very much required.
It is nice to study from Rakesh Jhunjhunwala sir... thank you sir for teaching VLSI apart from investing.
🤣🤣
@@jyotichhichhollia2492 😂 thanks for reminding me this joke. Hope u will get good marks in your exam 🌝
😂😂
😂
🤣 lmfao
50:20
One side is specified as source and other as drain just because of the voltage difference .as we all know that the source is grounded the side which has lower potential is known as source and the side with higher potential is known as drain.
Answer to the question asked at 24:28 --The one which is connected to higher potential (Vdd) is drain and the one which is connected to lower potential (vss) is source . It is called symmetric because rise time and fall time are equal, device ratio is unity.
This lecture is so brilliant! None of my college professors, or even other resources compare to this.
Excellent sir... crystal clear explanation... Thanks for your efforts... Thank you
Good explanation.. very clear. I have got one certificate. And i wish i could get another one. Thanks NPTEL...
nice explanation sir, i appreciate your efforts, may god give you all that you want in your life.
The title of every lecture should be properly specified so that their searchability increase while searching on RUclips and Google.
Yeah, absolutely correct good lecture lost its SEO content in google. Rather than searchability please specify SEO (Search Engine Optimisation)
Some lazy idiot at IITM, confident of a "permanent job", is making these third-rate titles.
#rakesh jhunjhunwala is a brilliant teacher 😅🙏👌
At 40:48, i think in depletion type n-MOSFET there is a physically implanted channel(as i have read from the books) . It does not have an N-type substrate as you quoted sir. But when there is a channel already present then how does the electric field modulate the channel which is the basic working of a MOSFET.
Excellent sir.. Thank you sir.
Best explanation ever.
What is the most suitable answer for the question asked at 24:32?
if mos structure is symmetrical then why one region is called source and another drain?
Because although they seem diagrammatically similar, at high frequency of operation, they do not exhibit the same capacitances (because they are made that way, they source being closer to the bulk). So yeah, sure for DC operation their switching action is symmetrical but not in computer circuits operating at GHz frequencies.
Best lacture 👍🏻
Very nice presentation sir , i really got some additional exposure than what i know already. Thank you so much sir , Have a great day sir. Srinivas , Hyderabad.
Excellent explanation Sir!. Really enjoyed the lecture
Explained very well 😃
Clearly explained from nook and corner
wonderfull explanation !!
Didn't realise but the green screen IS helping. The other IIT videos' dull background makes it tough to concentrate.
Very good explanation...
Great lecture sir
Sir please tell why do we have pre channel in depletion mosfet why not in enhancement mosfet?
SUPROBHAT GURU JI 🙏🙏
Excellent Explanation
Is the explanation of depletion mode mosfet correct?
This is very good lecture to understand. Sir how can I get depletion mode Ltspice model to verify IV characteristic
why we use bulk/substrate contact?
thanks u sir a lot , love u sooomuch ,tnx tnx
very nice lecture
sir please give the answer you asked for...they are saying we can interchange but unable to say why its on left and drain on right to gate of mosfet
sir please tell me how to get it on swayam or nptel because this course is not showing there
In n-type depletion mode mosfet the substrate is not n-type, if i am not wrong
Can anyone let me know that As the technology is upgrading day by day is it a good idea to go with these videos?
Sir, the "n-well" that you explained - it is ultimately the combination of NMOS and PMOS or anythng else?
N well is basically doping of n type electrons in a p type substrate
@my work Albert malvino
sir where can i get that ppt...
Do anyone know best lecture of nptel for vlsi testing and testability
sir pls explain clearly how cox and cdep are in series ?
What is the reference book followed in this course??
Design of Analog CMOS Integrated Circuits
Book by Behzad Razavi
sir still are you working in IIT Roorkee, sir could you please tell me
Can anyone plz tell me good lecture for digital communication and analog communication
Dear Sir,
In NMOS Transistor, Current doesn't flow from source to Drain terminal rather electron flows.
Isn't it same??
Electrons carry current
@@janimohammad9675 current flow in direction opposite to flow of electrons
right sir i was also confused
good discussion, most of the circuit analysis, we use the convention current was is based on "holes" so opposite of "electron". So, when we say S-to-D that is the "electron" current, in circuit analysis (textbooks), most of the time we are assuming the convention or "hole" current which so D-to-S current. It can be confusing.
Thanku so much sir
29:32 resume
Tq sir
15/09/24 Lecture 1 Done
Sir can i get notes of this?
30/7/2024 part-1
completed
Amazing
Sir I am Vinay, from telangana .Sir I have registered for cmos vlsi designing as my nptel course .Sir I had a doubt that some will complete their course fastly and some by some delay then,exam date will be fixed or based on completion we can write the exam ?
@@arunapotla7883 haa vachindhi
@@arunapotla7883 frustration lo joke chesa le ,job aa bokka aa 2 backlog lu vunnai
@40:00 onward....speaking faster and even faster...faster, faster, faster...this is a race, isn't it? Who cares if the students can't follow?
Geovanni Summit
Why don't you write even smaller? Then at least ants can understand semiconductors!
In 51 minute video right .....you try to teach well right ....but i can't get you right ....please make this lecture in hindi right ....but only if your hindi is right ....sorry sir ...right...
Learn English ...it will be beneficial for you ......
Writing a comment in English and asking for lecture in Hindi just to show yourself cool is not 'right'!