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@@maggiemeghana5216 bcoz in pal we have to take fixed or gates so for that we check which fn has big boolean fn so int his case y has three products so for that we have taken 3 and gates for each bcoz of fixed or gates all the fn i. E x, y, z we have a total of 9 gates
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@@EngineeringFunda ok Ill do that you deserve more than this . but pleas can you make a video about asynchronous sequential logic with examples. regards.
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Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
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Your Video lectures are awesome... Everything is explained in a very neat and tidy way. Please make a video on FPGA also... It think that's the only topic you have not covered Thank You
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Sir plzz...make lectures on electrical measurement subject as soon as possible...provide ur lecture materials as pdf in special websites....not only through app..
Hello sir good morning design a PAL circuit that compares two 2-bit unsigned binary numbers A=(a1,a0)and B=(b1,b0) and produces 3 outputs :X=1if A=B,Y=1if A>B and Z=1 if A
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Thanks again, we couldn't have pulled this off without your explanation sir☺
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But my doubt is how can I add exactly 9 and gates?, It haveing any rules?
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Sir, how to identify the number of AND gates in PAL?
3 for each maybe
Thank you so much sir. Such nice explanation and the playlists you made are the best one can learn from. ❤
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blessed to have you here!!
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How do we know ....How many AND gates have to take...?
Late reply but the max number of min terms times the number of outputs
@@nongmaithemavinash3977 thanks! 👍
@@nongmaithemavinash3977 not late ..here today and it helped 🎉🎉
Sir we should take same example??
Wha wah wah wahh......excellent × 9999🤩🤩🤩🤩🤩 thank u TOOO much sir.
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Neat and clear explanation.
Thank you sir
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Why did we take 9 AND gates??
@@maggiemeghana5216 bcoz in pal we have to take fixed or gates so for that we check which fn has big boolean fn so int his case y has three products so for that we have taken 3 and gates for each bcoz of fixed or gates all the fn i. E x, y, z we have a total of 9 gates
it is my best channel tank you much
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@@EngineeringFunda ok Ill do that you deserve more than this . but pleas can you make a video about asynchronous sequential logic with examples. regards.
how can we calculate the no of needed Programmable AND Gate is needed ?? here ,,,,,,,pls reply
Sir I will never forget your help
You're welcome! I'm glad I could help you understand the concepts of PAL!
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Thank you sir and keep helping us😊👍🏼
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Well explained sir clarified my doubts
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Thank you Sir.You made my life easier
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Thank you so much sir for the clear explanation
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Thanks sir,,,, your class is superb.
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Awesome sir👍👍👍👍
Love and happiness of students is my ultimate goal, God bless you 🙏, keep learning and keep progressing.
your explanation is very good sir
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Sir how you take 9 AND gates
Nice explained sir thank you sooo much
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In this PAL why 9 AND Gates are taken??
Thank-you sir❤
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Sir explain why you took 9 and gates
It is just example dear
why we have used 9 AND gates here even though the product terms are not 9?
Thank you for this video sir
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@@likitha8349 nuv Telugu kadha
very easy explaination
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Your Video lectures are awesome... Everything is explained in a very neat and tidy way.
Please make a video on FPGA also... It think that's the only topic you have not covered
Thank You
I will definitely try to make it
Here man take a bow🙏🙏
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Why 9 And gates ?
Because each term will have 3 AND gates
thank you sir
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Sir , Could you please provide us the video lectures on CPLD and FGPA ??
Thanku so much sir 🙏
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Sir plzz...make lectures on electrical measurement subject as soon as possible...provide ur lecture materials as pdf in special websites....not only through app..
Thank you so much ❤
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Hello sir good morning design a PAL circuit that compares two 2-bit unsigned binary numbers A=(a1,a0)and B=(b1,b0) and produces 3 outputs :X=1if A=B,Y=1if A>B and Z=1 if A
Partially few marks will be given and that is based on your teacher.
Thanks
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Sir how can we decide no. Of AND gates??
Sir Please explain the no of And gate use
please add software engineering, design and analysis of algorithm videoes
Sir on what basis you took so many and gates ??
Pls , i couldn't understand that
Based on logic one can utilize gates, it has fixed gates based on size, we should gates based on logic.
@@EngineeringFunda based on size of what sir ?
@@EngineeringFunda if we have y = 4 product terms , how many and gates will be there ??
Help pls
PLA
Y = 4 will get deployed on PLA,
You should ask how many will get used on PLA.
sir how we know how many and gates we should take?
What if product terms are more than three ?
Method will not change
Sir What are the differences between PLA and PAL, please reply sir...
Thanks sir
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Sir what if we don't draw fuse intacted AND gates? Should we necessarily draw them though we don't use them?
I have shown those which is used, practically there are many in PAL
good class
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Beautiful
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Sir ye theory me pucha jaye to yahi likhna he na sir. Plz giv3 me a riplay sir
Sir in step up cycloconverter how to force commute the scr please help its really imp
Sir,Where is programmable table?...😢
Sir hum ko kasy pta chaly gay kitnay and aur not gates kagnay hy
It's just example dear. You can take any example.
gOOD
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good sir
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How to Know , how many and gates are used .
BTW superb playlist
your welcome
how to decide the number of and gates to be drawn sir.
Used gates depends on logic, you can draw as many aa you like to draw.
Me EMFT or Digital ap se pada raha hun beat ho ap ab jldi Analog bhi do sir
Great can you make a video about GAL and FPGA?
In my 1st sem.....i wrote these which I hv studied here.....i will get mark or not??
Which you have studied here, will give marks for sure 👍 😀
Isme no of and gates and or gates kaise ye to bta do sir
Pta kaise chalega hme aap ne bas to fix fix keh k bna diya btaya he nhi kaise liye
3 input so 9 is maximum output and gates you can get, so he used 9 and gates, 3 with each or gates
🙏
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sir logic families bhi pdaoge na...
it will come after VLSI playlist
Sir can i have detailed explanation of PAL
I have this only right now
Sir Analog electronic k complete vedio Karea uploaded jaldi ..plz uploaded analog electronic vedio
For 4 variables sir
THE VALUE OF X IS WRONG...SIR ...IT SHOULD BE B(A'+C)
It is perfectly correct dear
@@EngineeringFunda plz explain sir
Kal ka paper sorted 😁😁
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i got confuse literally what i learned from books and you
You copy Neso Academy video
Ditto copy..
I don't copy anyone, you should think before you insult any professor.
Thanks sir
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