ZX Spectrum 80K Upgrades Part 2 - What's going on here then???
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- Опубликовано: 20 окт 2024
- More reverse engineering, this is essentially part 2 of the 80K mod video you saw recently.
Thanks Colin for loaning me this!
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Go read Chris Smith's book on the ULA
www.amazon.co.... (No affiliation)
That was a very detailed bit of reverse engineering. Well presented too. As I understand it, this is how the refresh arrangement works....
The DRAM chips are specified with a refresh interval that guarantees data retention at worst case temperature and operating voltage. The temperature part is important here, since if the maximum rated temperature for a commercially specified chip is 70 degrees Celsius, the internal leakage is a small fraction of that at lower temperatures, say, 40 degrees. That allows the refresh time for each row to be massively extended (10s of milliseconds can be absolutely fine at room temperature). The next point is that the DRAM chip doesn't care if some rows are refreshed more often than others, provided that they are all refreshed often enough. So what the designers did was allow the bit in the row address that is generated by this logic to be at a zero state for well over 128 refresh cycles, and then to be at a one for well over 128 refresh cycles. Note also that the number of cycles at each state of the oscillator will depend on the capacitor and resistor in the crude timing circuit and also on the NAND gate chip.
If we pretend that the generated bit was the most significant row address bit (it really doesn't matter which, but this makes the visualisation simpler) then as an example, the DRAMs may refresh rows 0 to 127 and again from 0 to 83 (somewhere random). The oscillator output changes state making the generated bit a one and the next refresh cycles are from row 84+128 (= row 212) to row 255 and then from row 128 to row 236 (another random choice which is more than 128 cycles from the staring point). To do that he Z80 refresh counter has counted from 84 to 127 and then from 0 to 108. Then the oscillator switches back and the refreshes continue from row 237-128 (so really 109) up to 127 and then from row 0 to 127 and then 0 to row 63 (somewhere else, also fairly random). And so it carries on - each burst of cycles may be of different length since it also depends on the instruction mix, but the DRAM doesn't care, because every 10ms or so, every row will have been refreshed at least once, and because the chips are not at maximum temperature the data is still safe.
It's a very clever scheme that they have used, using minimal logic, but due to the actual operating temperature of the chips (probably always below 50 degrees) then it works and does so reliably. I hope this helps. BTW, I was a logic designer in the 1980s and did design a number of boards using DRAMs between 64k and 4M in capacity - I still know how these things worked back then - very much simpler than modern DDR style RAM chips.
Thanks for the excellent info you are clearly an expert, and good to know that this seems to be in the realms of acceptable usage of these chips. They will get quite warm though in an issue two, being so close to the heatsink. People recommend fitting capacitors in this area of the board with a temperature rating over 100°
@HappyLittleDiodes If the DRAM chips get to 100 degrees I would expect problems, but it's likely mostly the heat sink, and the chips would be just a bit cooler. Using capacitors with a high temperature rating helps ensure they last longer, and the 1980s and 90s were a time when there were many poorer quality capacitors on the market. One other thing - Sinclair loved to take chances with component tolerances in pursuit of a cost reduced design, knowing that in most cases things would turn out fine, and that allowed them to make a number of design choices that I would never have been allowed to make when designing commercial hardware where reliability and data accuracy were a key consideration.
Thanks for another well constructed and steady video!
You have a real talent for making them!
Thanks that's very kind
Wow, a lot to digest. I'll need to rewatch again, probably small sections at a time. Excellent video that is jam packed with info.
IM2 should work fine if the vector table is properly constructed. On the Z80 Interrupt mode 2 works like this: you have a vector table of up to 128 entries (a total of 256 bytes as these are 16 bit addresses) that must be page aligned (this is the intended use case, but the mechanism can be abused manipulating the bus address when an INT happens), you place a value into the register I, that byte is the high byte of the vector table's address, then, when an interrupt happens the CPU reads the bus and uses the value of I and the value of the bus to read an entry of the vector table and finally jumps to the address that was held in that vector table entry. On the speccy as you cannot guarantee the value of the bus at a given moment usually the vector table is composed of 257 bytes all with the same value, (for example 0xEE, that would guarantee that it always jumps to 0xEEEE) . Said that, if you place the vector table into the lower ram, or into the upper ram and write the vector table in both banks (and the interrupt routine if it is placed into the upper memory) it should work. It could even be abused, you could create two different vector tables and switch the banks if you want to do a fast change of the interrupt handler routine.
Interesting! Thanks for the detailed info, good to understand it a bit better
Brilliant Jim.
This may take a couple of watches to get my head around it. Very well explained though.
Thank you.
I had one of these boards fitted to my frankenstein ZX Spectrum in the 80's. I recently refurbised the spectrum and just removed this board because I never found anything that I could do with it at the time, and had completely forgotten what it was come refurbish time. It will now be in a draw somewhere.
Do you have any paperwork with it by any chance?
sorry, no. I didn't even remember what it did until I saw your video. Sorry.
@pepperm16 no worries! Worth a try :)
@@HappyLittleDiodes also, I guess that the board requires DRAM with both halves working, not the ones fitted onto the spectrum that have one half known faulty at assembly time.
if sinclair had included an upper ram CS line on the expansion slot (there is at least one spare one) , ram expansions would be much easier and could be done completely externally !
I'm inclined to agree with you!
@@HappyLittleDiodes its easy enough to mod the upper ram circuit to add a CS but has unfortunate side effect it disables refresh, so the ram wouldnt retain data while deactivated, you'd need additional circuitry in the external expansion to turn the internal ram back on during refresh cycles! or add extra gates in the spectrum to do it, but thats less simple 😉
3:33 'sca' not 'scd'. The upper part of the lower case 'a' is feint, but clearly there.
Ah yes that's a good spot, might help the search
hmm,,, convoluted way to enable 256 refresh cycle ram to be used, and yes i wouldnt have thought thered be enough refresh cycles done in the refresh period with inverting bank select at 50hz?! maybe they found in practice it did work..!! also use OUT 1 instead of 0, so it doesnt affect border colour, or, any odd address with A1 low ...
That was my thought, maybe the refresh just worked. Like the open collector gate that feeds another input without a pull up resistor!
@@HappyLittleDiodes LS inputs have internal pull up resistors, standard TTL inputs are actually an emitter of a transistor, so will also self pull up high(input transistor off) probably wont work with modern HC or HCT 😉
@andygozzo72 fantastic
@@HappyLittleDiodes manufacturers didnt really recommend leaving inputs floating, especially if not used, but many circuits did
@@andygozzo72 The open entrances in particular have led to many problems that are not always understandable. Most of the time the circuit worked ( approx 99% ), but not always.
That's why I always check what the open entrance is doing. At the OR entrance I place it parallel to the other entrance. Otherwise (usually) against ground.
If the input is to be operated on an open collector, I put a 1K resistor on the input (at HC(t)) 10k.)
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