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Thinking of getting this kit for my harlequin. Would you recommend hot air for this, would the PCB take it?

i have 2 'toastracks' one with mask rom one with eprom, dunno if one is more common than the other!i

If something were able to encapsulate the sound of melting, this is it!

somehow missed this one so sorry for the late comment. well done on the build it looks great

Turbo Killer!

I like it if I can find a furby I havent seen one of those for 20 or more years

where could I find a Furby besides Flea bay?

To do the same on a C64 would the user port be better

hey I would like to do something like that with a C=64 I guess I need to find a furby on ebay, very cool

nice work

yes I like that tight tolerance to keep the component in place that helps a lot

kind of neat to see how the vic20 and C64 keyboard came from neat

the background chuckling is the best part :)

I'm unfamiliar with that piece, but I would like to know more about that particular build, if possible?

Daisy, Daisy...

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I love the composed "okay" at the beginning in contrast with how it turns out 😂

I've got an Omni, love it, great little machine, what do you think?

Everyone has got to start somewhere! :D

😂😂😂😂😂😂😂😂😂😂😂😂

Oh this made me laugh!!! so funny :)

That was a very detailed bit of reverse engineering. Well presented too. As I understand it, this is how the refresh arrangement works.... The DRAM chips are specified with a refresh interval that guarantees data retention at worst case temperature and operating voltage. The temperature part is important here, since if the maximum rated temperature for a commercially specified chip is 70 degrees Celsius, the internal leakage is a small fraction of that at lower temperatures, say, 40 degrees. That allows the refresh time for each row to be massively extended (10s of milliseconds can be absolutely fine at room temperature). The next point is that the DRAM chip doesn't care if some rows are refreshed more often than others, provided that they are all refreshed often enough. So what the designers did was allow the bit in the row address that is generated by this logic to be at a zero state for well over 128 refresh cycles, and then to be at a one for well over 128 refresh cycles. Note also that the number of cycles at each state of the oscillator will depend on the capacitor and resistor in the crude timing circuit and also on the NAND gate chip. If we pretend that the generated bit was the most significant row address bit (it really doesn't matter which, but this makes the visualisation simpler) then as an example, the DRAMs may refresh rows 0 to 127 and again from 0 to 83 (somewhere random). The oscillator output changes state making the generated bit a one and the next refresh cycles are from row 84+128 (= row 212) to row 255 and then from row 128 to row 236 (another random choice which is more than 128 cycles from the staring point). To do that he Z80 refresh counter has counted from 84 to 127 and then from 0 to 108. Then the oscillator switches back and the refreshes continue from row 237-128 (so really 109) up to 127 and then from row 0 to 127 and then 0 to row 63 (somewhere else, also fairly random). And so it carries on - each burst of cycles may be of different length since it also depends on the instruction mix, but the DRAM doesn't care, because every 10ms or so, every row will have been refreshed at least once, and because the chips are not at maximum temperature the data is still safe. It's a very clever scheme that they have used, using minimal logic, but due to the actual operating temperature of the chips (probably always below 50 degrees) then it works and does so reliably. I hope this helps. BTW, I was a logic designer in the 1980s and did design a number of boards using DRAMs between 64k and 4M in capacity - I still know how these things worked back then - very much simpler than modern DDR style RAM chips.

I had one of these boards fitted to my frankenstein ZX Spectrum in the 80's. I recently refurbised the spectrum and just removed this board because I never found anything that I could do with it at the time, and had completely forgotten what it was come refurbish time. It will now be in a draw somewhere.

Wow, a lot to digest. I'll need to rewatch again, probably small sections at a time. Excellent video that is jam packed with info.

flux on the joins to desolder helps a lot

if sinclair had included an upper ram CS line on the expansion slot (there is at least one spare one) , ram expansions would be much easier and could be done completely externally !

hmm,,, convoluted way to enable 256 refresh cycle ram to be used, and yes i wouldnt have thought thered be enough refresh cycles done in the refresh period with inverting bank select at 50hz?! maybe they found in practice it did work..!! also use OUT 1 instead of 0, so it doesnt affect border colour, or, any odd address with A1 low ...

Brilliant Jim. This may take a couple of watches to get my head around it. Very well explained though. Thank you.

Thanks for another well constructed and steady video! You have a real talent for making them!

3:33 'sca' not 'scd'. The upper part of the lower case 'a' is feint, but clearly there.

IM2 should work fine if the vector table is properly constructed. On the Z80 Interrupt mode 2 works like this: you have a vector table of up to 128 entries (a total of 256 bytes as these are 16 bit addresses) that must be page aligned (this is the intended use case, but the mechanism can be abused manipulating the bus address when an INT happens), you place a value into the register I, that byte is the high byte of the vector table's address, then, when an interrupt happens the CPU reads the bus and uses the value of I and the value of the bus to read an entry of the vector table and finally jumps to the address that was held in that vector table entry. On the speccy as you cannot guarantee the value of the bus at a given moment usually the vector table is composed of 257 bytes all with the same value, (for example 0xEE, that would guarantee that it always jumps to 0xEEEE) . Said that, if you place the vector table into the lower ram, or into the upper ram and write the vector table in both banks (and the interrupt routine if it is placed into the upper memory) it should work. It could even be abused, you could create two different vector tables and switch the banks if you want to do a fast change of the interrupt handler routine.

Nice. A couple of questions ... 1. Why does the EPROM need a sticker? 2. What's the danger of putting the board in a vice? Does flexing the board not cause issues? A final weird one ... what do you do with the legs you snip from the components? Do they have any use at all? I'm not a fan of waste.🙄

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Hi! I'm enjoying a lot your microdrive videos. You see what happens in your video that, while formatting, the screen turns white and the black stripes stop? That's happening to me, the CAT never ends (must be stopped), and while formatting, stripes appear like for 10 seconds but then the screen goes white and the microdrive keeps turning forever. Do you have an idea of where the problem could lie? I've tested several microdrives. Thanks!

BRILLIANT! Absolutely brilliant video! It would be nice a small circuit board to plug it directly onto the Speccy motherboard and then pop on int all the involved chips, to avoid this mess of wires... Unfortunately I'm not aware of software to take advantage of this 80K trick. Maybe some utilities and multilevel loading games could have used this feature. This is where the Speccy 128K came handy.

The manual focussing is a feature, not a bug. Most of these small phone-mounted cameras are not autofocus (in fact I'm not sure autofocus exists at all in the world of thermal cameras) - they're fixed focus. This works fine for distant objects as with a cheap film camera but if you want to focus on something close like a PCB you're stuck. A workaround is a supplemental macro lens but that's a bit of a faff and forces you to focus by moving the camera. It seems odd that topdon advertise it as having a longer range (most are optimum at 5m) but it's actually closeup that's really interesting. What about the chunky block that was also in the case ? Is that a mounting bracket ?

😮😮😮😮😮jesus

Intel do the same with their chips nowadays. The ones with all cores working are intel 10 ( I`m not an expert ) and the ones with less cores working sell as lower chips.

That ITT chip could be original, Sinclair would mix up chips in production, so you easily could have had the end of one tube in production, and the next tube grabbed was the ITT one, or that ITT chip was the last, and then the assembler started with a new tube after putting the last one in.

As others have pointed out, this will only work correctly if your stack pointer is NOT in the bank switched area of RAM, which means the BASIC program must be in the lower 16K of RAM. As I understand it, this means that BASIC won't be able to directly access the upper 64K (two banks of 32K) for BASIC programs. Also, any machine code routine which may be running in the upper 32K would not be able to use the other 32K directly since switching to it would stop the CPU from accessing the machine code program which would cause a crash. The best use you could probably make of the upper banks would be as a "RAM drive" so that programs of up to the free memory size can be transferred out of one of the high memory areas into the lower 16K, replacing the program which was there. A completely machine-code program may be able to make use of the upper two banks by loading one part of the program into one bank and another part of the program into a different bank and then using a "handoff" routine located inside the lower 16K to perform both the bank switching and the jump into the "second half" of the machine code program. With some clever programming and positioning of code, it may be possible to load what is effectively one program into two different banks of memory, and have a conditional which either jumps past the bank switching or not, depending upon the outcome of a test. Done right, this would save space and prevent crashes, but it's a hassle and is not something which would be supported by any assembler in existence. For example, bank 0 has a test, a jump to the skip location if the test succeeds, the bank switching code if the test fails, then the code which is skipped to if the test succeeds. In bank 1, at the exact same location as the code for if the test succeeded, is code to be run if the test failed. If the test succeeds, the bank switching code is skipped and the "test succeeded" code gets run. If the test fails, the bank switching code gets run and as soon as the last instruction of the bank switching executes, bank 1 becomes active and the next instruction in there is the first instruction of the "test failed" code. All of which is a long, long way of saying that using this extra RAM bank is a hassle and requires some decidedly non-trivial programming tricks. All the same, it's enjoyable to see an old computer used in a new and innovative way. EDIT: Or replace the ROM BASIC with your own version which is bank-switching aware. But that's also non-trivial.

Thank you for the RAM explainer. I know nothing about this (and computer repair in general) and it really helped to see how memory is structured in a very clear and easy to understand way. I feel your frustration with solder joints not clearing, I have damaged a few by working past my concentration , not taking a break and working on something else. A moogun sorted a lot of that out for me.

Can it find water leak? I have plumbing problem in bathroom, drain pipe is under concrete and tile floor and water pipe is inside brick wall.... Also advice if it can detect animal inside car or van that is invisible to human.

Can you get 128kb ram chips? I need at least 2 and possibly 100! For sam she's 6mhz z80b

Could you make a technical description of the spectra interface please ? Think she has 32kb of video ram

Intresting :D ofcourse a flipflop to keep the state, bank switching was and is awesome. might reuse this knowledge for my own computer builds :D is there known software that can make use of this extra ram?

Great video! I'll build it! You're using OUT to switch banks, shouldn't be IORQ instead of MREQ?

you didnt explain the difference with OKI rams, for those that want to know, basically it swaps the order of the selection of A14 and the ?? bits in the upper multiplexer chip 2 ... one brand has a bad column address, the other a bad row, cant remember which for sure but think the TI ones are bad column