#32 Linear voltage regulators architectures

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  • Опубликовано: 29 дек 2024

Комментарии • 17

  • @jagdishpanpalia7482
    @jagdishpanpalia7482 3 года назад +1

    Excited for the upcoming detailed videos on each architecture.
    Eagerly waiting 😃

  • @abhiruplahiri1
    @abhiruplahiri1 3 года назад +2

    Good stuff as always!

  • @RohitSingh-qe6fp
    @RohitSingh-qe6fp 2 года назад +1

    Good explanation

  • @sudhanshusingh1234
    @sudhanshusingh1234 2 года назад +2

    Good to understand

  • @98505177229850590818
    @98505177229850590818 2 года назад +1

    How did u get VIN MIN IS vout plus 1 for nmos regulator ?
    Also can u tell whether pmos or nmos works in linear or saturation mode during regulating ?

    • @analogsnippets
      @analogsnippets  2 года назад

      NMOS regulator needs gate voltage higher than output voltage. Since threshold voltage of nmos is ~0.7V, I have assumed we would need 1V above vout.

    • @analogsnippets
      @analogsnippets  2 года назад

      For most part nmos and pmos work in saturation. For higher load current pmos may enter linear but a good design would try to limit it to corner cases. For nmos if amplifier is supplied by vin then nmos will always be in saturation region.

  • @pikulsarkar7537
    @pikulsarkar7537 3 года назад +1

    Can you add digital ldo to the list and discuss in details in one video?

    • @analogsnippets
      @analogsnippets  3 года назад

      What do you mean by digital ldo? The use case that I gave in video?

    • @pikulsarkar7537
      @pikulsarkar7537 3 года назад +1

      @@analogsnippets No. Loop will be digitally controlled with power mos acting as switches.

    • @analogsnippets
      @analogsnippets  3 года назад

      I have only read about it, not actually designed it. So not an expert on this topic.

    • @abhiruplahiri1
      @abhiruplahiri1 3 года назад +2

      Hi Pikul, here is a link to a simple work we did for dig ldo: A. Lahiri, S. Bansal, N. Bansal and M. S. Hashmi, "Digital LDO with analog-assisted dynamic reference correction for fast and accurate load regulation," 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, pp. 767-770, doi: 10.1109/MWSCAS.2017.8053036

  • @yunusdification
    @yunusdification 2 года назад

    You would only need Vth in the source follower case.

    • @yunusdification
      @yunusdification 2 года назад

      Infact there can be benefits in PSRR if you use the source follower LDO

    • @vladimirvolokitin8367
      @vladimirvolokitin8367 2 года назад +1

      @@yunusdification only if you have very good PSRR for your Amplifier. On other hand for PMOS LDO amplifier PSRR should be ZERO

    • @yunusdification
      @yunusdification 2 года назад

      @@vladimirvolokitin8367 yeah good point. the first pole of opamp becomes the dominant pole. So in fact to adjust that pole you add cap at output of opamp to compensate the loop. This cap should also help the PSRR.

  • @waferlayout
    @waferlayout 11 месяцев назад

    I am new😊
    LDO voltage😊