Aries CXL™ Smart Retimer Demo: CXL Ecosystem Interop with Intel and Synopsys

Enabling Robust CXL™ Connectivity for Intel Sapphire Rapids CPU-based Systems with Synopsys DesignWare CXL Controller IP
In this video, Astera Labs VP of Products Casey Morrison demonstrates the industry’s first fully formed CXL™ link between a root complex, a retimer and end point IP. Specifically, the interoperability demo features an Intel Sapphire Rapids CPU, Astera Labs’ Solstice 3U Riser Card with two Aries CXL Smart Retimers, and the Synopsys DesignWare CXL Controller IP, showing successful transmission of CXL.io, CXL.cache, and CXL.mem transactions.
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