Mod-02 Lec-04 Analysis of Synchronous Sequential Circuits

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  • Опубликовано: 11 янв 2025

Комментарии • 2

  • @gadewaronkar
    @gadewaronkar 7 лет назад +1

    I think there is some error in truth table for mod-6 with UP/DN functionality.In both cases present state counts the same sequence.For UP/DN=0 counter should down count

  • @maheshdharshanala7483
    @maheshdharshanala7483 7 лет назад

    sir in practical there is a possibility of combined skew in (data path and clock path) how do we analyze that?