Tutorial XADC IP - Vivado 2017.2 - Arty Board

Ensina como desenvolver e rodar o bloco IP XADC no vivado 2017.2, utilizando a placa Arty

[@shwetaj6622]

Thank you for the informative video, could you tell what frequency signals you are giving as input? cause I tried using 1khz frequency signal and the waveform is coming distorted. The JTAG apparently can take only 1 sample per second. Is there a way to view higher frequency signals in the XADC system monitor?

[@MuradJamalieh]

Thank you it worked perfectly was able to go to 1.000 V max on the ADC input. One should first program the FPGA and then the XADC monitor dashboard will show the correctly acquired values.

[@sparky173j]

Thankyou. This helped me get my XADC working (using AXI4 lite interface to a soft core)

[@depodotes]

Can you please send me your project(XADC AXI4 lite interface to a soft core), I have been looking for it for a long time. I tried but I am stuck. thank you.

[@onecircuit]

I notice your analog readings only go to 0.380V maximum. What are your inputs when you reach that level? 3.3V?

[@eladiobarrioquerol5498]

he reads 0.99 at 3.3V input (19:00), usually the dev. boards have
a resistive divider and a low pass filter before the SoC input

[@kalyankumar901]

can you please tell how to use in drp mode

[@davidgordillo5635]

disculpa tiens el poryecto de xadc con microblaze

[@kramer3d]

You don't even need to generate a bit file in order to access XADC system monitor. Bad tutorial

[@ВладиславКузнецов-ф6ж]

make better

[@chrystopherborba365]

Okay, i appreciate your comment