Z8S180 Breakout Board Testing Pt. III

Booting code that was assembled from Z80 source code and loaded into a block RAM and testing the SRAM chip.
Check out the discord: / discord
Github repo for this CPU board: github.com/johnwinans/2067-Z8...
Github repo with the FPGA board that this plugs into: github.com/johnwinans/2057-IC...
Github repo for the Verilog Examples: github.com/johnwinans/Verilog...
Z80 Nouveau Playlist: • Z80 Nouveau
FPGA board video playlist: • FPGA
You can support this channel on Patreon! / johnsbasement
Music used in this video (Vibe Tracks, Alternate) was downloaded from the RUclips Audio Library.
#verilog
#z80

[@vasileceteras]

This is fun, and educative. The best way to learn something like verilog.
Now I really want to order those two boards, build them and follow along!

[@JohnsBasement]

Thanks! You should also pop into the Z80-Retro discord and see what is going on there. A few have already been talking about their progress & offering tips that are good to know!

[@captaindunsell8568]

The $readmemb and $readmemh are ascii representation of binary and hex respectively with space or newline are separators.

[@JohnsBasement]

Thanks!

[@EngineeringVignettes]

I admit I have not tried this myself.. but it should be possible to get synchronous block RAM to emulate asynchronous RAM by placing state-based delay (counters) between the bus signals and the internal RAM.
eg. "on falling edge of RD, count to n then assert blockRAM data at address A". Internal Block RAM and the counters are running at the internal FPGA fabric bus speed.
This could also be used to setup wait-states for tuning different CPU bus speeds.. emulating certain RAM speed ratings etc..
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Nice work of the RAM testing, looking good :)
Cheers,

[@JohnsBasement]

Thanks!
Yes, I hope something like this will work. Plus, when we start looking at DMA and cycle-stealing to support devices like the SD card and a video display, we will want to look at this same sort of thing for the SRAM too!

[@timgordon2943]

I found the same thing when playing with Xilinx initialized RAM blocks- if you don't write the VHDL correctly, it would synthesize the memory in logic blocks instead of the built-in RAM :P

[@JohnsBasement]

Yeah. When creating synthesizable circuits with verilog, we have to always keep in mind that we are an inch away from the netlist.