Advanced RISC-V Verification Technique Learnings for SoC Validation

Advanced RISC-V Verification Technique Learnings for SoC Validation
The verification of application-level RISC-V cores require specialized techniques and approaches previously the purview of Arm, Intel and other processor companies. The open and customizable RISC-V cores have led to many new processor development teams with unique microarchitectural approaches that require extensive verification.
RISC-V verification requires specialized techniques not often used by general verification teams.
RISC-V cores must be verified for their interaction with the broader system to find obscure but critical problems.
Learnings from these new techniques may be applied to general SoC verification and find corner-cases not detectable in traditional system validation.
Adnan is the founder and CTO of Breker and the inventor of its core technology. Noted as the father of Portable Stimulus, he has over 20 years of experience in functional verification automation, much of it spent working in this domain. Prior to Breker, he managed AMD’s System Logic Division, and also led their verification team to create the first test case generator providing 100% coverage for an x86-class microprocessor.