It was a very clear explaination, thanks a lot. I have one question though: at lesson, my teacher said that (while drawing the MIPS pipeline architecture) the branch control signal is produced once the mem stage has started. Does this mean that the end of the mem stage has to be waited to know the correct PC value (and if the branch happens ) ? Does it mean that the next (correct) instruction fetch is done after the mem stage has ended?
For any branch instruction the next instruction is known to us right after EX in normal cases i.e. it will give 2 stall stages but if you use something to compute the next instruction a bit earlier you can use comparator at ID which will enable us to know the next instruction right after ID i.e. 1 stall stages which is better. I know its a bit late XD
So basically stalling will always make the code run slower, but if we at least predict that our branch will not be taken, we reduce the number of stalls our code experiences, ultimately improving performance? Is that idea?
But when you do a branch instruction doesn't it read the status registers(set by previous (S) instruction) to determine whether to take that branch or not?
+jmunoz96 Branch has two types and they are beq = branch equal and bne = branch not equal. beq, compares between two registers and if these two registers hold the same value, we branch (jump) to the specified label. bne does the same thing, but in reverse.
thanks! this was very clear and helpful explanation
Thank you so much for this.
Really good video! Thanks!
Very good explanation thank you a lot!
It was a very clear explaination, thanks a lot. I have one question though: at lesson, my teacher said that (while drawing the MIPS pipeline architecture) the branch control signal is produced once the mem stage has started. Does this mean that the end of the mem stage has to be waited to know the correct PC value (and if the branch happens ) ? Does it mean that the next (correct) instruction fetch is done after the mem stage has ended?
For any branch instruction the next instruction is known to us right after EX in normal cases i.e. it will give 2 stall stages but if you use something to compute the next instruction a bit earlier you can use comparator at ID which will enable us to know the next instruction right after ID i.e. 1 stall stages which is better.
I know its a bit late XD
Thanks
So Clear
So basically stalling will always make the code run slower, but if we at least predict that our branch will not be taken, we reduce the number of stalls our code experiences, ultimately improving performance? Is that idea?
So is it just after the ALU stage can we figure it out what the correct instruction is? or should wait until the end of MEM stage? Thx
Wait, so the video just finishes like that? He introduced a very interesting problem in the end ;..;
Thanks very much mate
Nice and clear. What would be the "mem" stage tho?
+xPa7r1cKx It stands for the "memory" stage where it is used mostly by store and load word instructions.
Thanks very helpful :)
why do u add 4? i know thats the word length for the instruction. but whats the instruction?
X2
and what would be an example of correct instruction @2:42? plz help
It could literally be anything...
But when you do a branch instruction doesn't it read the status registers(set by previous (S) instruction) to determine whether to take that branch or not?
I'm so confused, didn't find this helpful. All I wanted was to understand how a branch works.
+jmunoz96 Branch has two types and they are beq = branch equal and bne = branch not equal.
beq, compares between two registers and if these two registers hold the same value, we branch (jump) to the specified label.
bne does the same thing, but in reverse.
Nice hand