2021_포스텍 전자회로1 24강 온라인수업, CMOS static logic circuit, CMOS inverter, logic threshold voltage, NML NMH

2021_포스텍 전자회로1 24강 온라인수업, CMOS static logic circuit, CMOS inverter, logic threshold voltage, noise margin VIL VIH NML NMH, dynamic power dissipation, ring oscillator, propagation delay time, tpHL tpLH, RON CL log2, static logic has DC path between VDD and Vout or VSS and Vout at steady state, string to coupling noise through capacitor