Thank you so much sir...I really dont have any idea about verilog but your explanation is outstanding and I learnt something today and I get lot of satisfaction ......waiting for more videos sir
This very unfortunate, views are 11k but likes are just 160. So please understand how much effort to put to maka a video. Who is wached this videos those are must and should be likes those video. 👍 🙏.
Thank you very much for your concern. I upload the content just to help freshers to learn vlsi related content conceptually and free of cost. Many training centre teach crap to freshers and charge a lot which is matter of concern. When I upload content i never even check how many views or likes my videos are getting. I always try to give the best content and not just theory. I will keep doing it in future also as I love sharing my knowledge. Even one individual learn something new from my tutorial then also I will feel very proud. I am uploading because of all of you. So keep learning and I will keep uploading content.Thanks.
At 13:21 e is wire and reg both how .... Because in above e expression e is already wire datatype by default but then on the very next line we made e reg type .... Also what if we further process this e variable then how will compiler knows that in which e(either wire or reg) we are dealing operations
By default every input and output port is wire. Say output e ; // it's a wire by default// only created a port // it's now unconnected wire e; // now declared e as wire so telling to compiler that it's data type is net type reg e ; // now telling compiler e as a storage component (flip flop) But as alredy we have taken e as both wire and reg so compiler shows error. Hope it helps
bhaiya as you didn't declare c1 and c2 and sab so it show error or not ?? just question from beginner as in interview he asked me this question and at that time i am not know about verilog please give answer with reason
Wire is something which allows signal to flow through it or which drives signal from one point to another and which can not store data. Hope you understand from above mentioned point. If you don't get it then please elaborate your query more so that I will be able answer you more correctly.
reg is used when something is assigned in a procedural block(always and initial). Wire is used in continuous assignment (assign) So it depends on how you use these to assign values. Wire is used to model combinational logic and reg is used for both sequential and combinational logic. So it's about when to use.
Nested modules not possible in verilog. But we can use port declaration of one module inside another module and this is called instantiation of module.
Thank you so much sir...I really dont have any idea about verilog but your explanation is outstanding and I learnt something today and I get lot of satisfaction ......waiting for more videos sir
Thank you for your appreciation. You can learn all the concepts of verilog and related concepts from this channel. Happy learning.
This very unfortunate, views are 11k but likes are just 160. So please understand how much effort to put to maka a video. Who is wached this videos those are must and should be likes those video. 👍 🙏.
Thank you very much for your concern. I upload the content just to help freshers to learn vlsi related content conceptually and free of cost. Many training centre teach crap to freshers and charge a lot which is matter of concern. When I upload content i never even check how many views or likes my videos are getting. I always try to give the best content and not just theory. I will keep doing it in future also as I love sharing my knowledge. Even one individual learn something new from my tutorial then also I will feel very proud. I am uploading because of all of you. So keep learning and I will keep uploading content.Thanks.
At 15:23 what is "sab" on line 4,5 we haven't declared "sab " as input or output then how did we used it ??
You explained very clearly.thanx
Good one...
Thank you sir from m
Kerala
Welcome. Happy learning.
Very good explanation. Keep going
Thank you.
At 13:21 e is wire and reg both how ....
Because in above e expression e is already wire datatype by default but then on the very next line we made e reg type ....
Also what if we further process this e variable then how will compiler knows that in which e(either wire or reg) we are dealing operations
By default every input and output port is wire.
Say
output e ; // it's a wire by default// only created a port // it's now unconnected
wire e; // now declared e as wire so telling to compiler that it's data type is net type
reg e ; // now telling compiler e as a storage component (flip flop)
But as alredy we have taken e as both wire and reg so compiler shows error.
Hope it helps
Really helpfull
Good to hear, it helped.
bhaiya as you didn't declare c1 and c2 and sab so it show error or not ?? just question from beginner as in interview he asked me this question and at that time i am not know about verilog please give answer with reason
Yes, you are correct.
I have forgotten to declare those variables. Sorry.
I have already mentioned it on comment section.
Thanks
hi sir. wire =connecting 2 components. then how can "b" is declared as a wire? . b is a constant or wire ?
Wire is something which allows signal to flow through it or which drives signal from one point to another and which can not store data.
Hope you understand from above mentioned point.
If you don't get it then please elaborate your query more so that I will be able answer you more correctly.
Sor verilog coding ke liye sabse best tool kaunsa h doesn't matter padi ho na ho clg id se chala lunga ...
Please batae sir
For students, free tools you can download. XILINX ISE and Modelsim. Students free version are available. it's enough for all your needs.
in full adder design, we didn't declare sab, c1, c2. My doubt is can't we get an error like declaration error
You have to declare it as wire. I have missed to declare it.Sorry.
But I think it didn't show error during compilation.
Thank you for giving immediate response sir
Sir,
One more doubt is If i prepare through all your videos.
Is it enough to ready for the interviews??
Sir If we don't register the output, is it raise error ?
reg is used when something is assigned in a procedural block(always and initial).
Wire is used in continuous assignment (assign)
So it depends on how you use these to assign values.
Wire is used to model combinational logic and reg is used for both sequential and combinational logic.
So it's about when to use.
@@ComponentByte thank you sir..😊❤
is nested modules allowed in Verilog code ?
Nested modules not possible in verilog. But we can use port declaration of one module inside another module and this is called instantiation of module.