Prof. Nauta I did argue against your post on Linkedin. The current crop of available RFSOCs are highly limited to around 4 GSPS for I and Q. However There are ways to phase stagger ADC sampling clocks to achieve 16 GSPS. by placing the sampling edges at different points within a 360 degree space. TI has such a 4 ADC architecture . But entirely getting rid of LNA-Mixer will take at least 5-10 years,. The WiFi 7 support 320 MHz now. But cost is a huge huge factor for RFSOCs so to make a change to a 2nm process for volume FPGAs will take huge investments. Quantization noise for an ADC directly connected to the antenna is a related but different question. Its not an area many people deal with but the theory is there - Gray and Neuhoff.
Thank you so much professor. This helped a lot. 😁
Prof. Nauta I did argue against your post on Linkedin. The current crop of available RFSOCs are highly limited to around 4 GSPS for I and Q.
However There are ways to phase stagger ADC sampling clocks to achieve 16 GSPS. by placing the sampling edges at different points within a 360 degree space.
TI has such a 4 ADC architecture . But entirely getting rid of LNA-Mixer will take at least 5-10 years,. The WiFi 7 support 320 MHz now.
But cost is a huge huge factor for RFSOCs so to make a change to a 2nm process for volume FPGAs will take huge investments.
Quantization noise for an ADC directly connected to the antenna is a related but different question. Its not an area many people deal with
but the theory is there - Gray and Neuhoff.