SPI Master with Chip-Select in FPGA, Verilog Code Example

[@frederickadom8203]

How can i connect the slave and master together

[@varunsharma3860]

@nandland @Russell
Hi, First of all I would like to thank you for making such wonderful videos explaining important protocols. I’ve been following your channel for about an year or so now. It has really helped me build my digital logic concepts 👍
I have a couple of questions regarding this SPI module:
1. Do you treat i_TX_DV as write_start or read_start command? Meaning you start SPI cycles whenever you receive i_TX_DV pulse?
2. If it is just a read operation, would CS be asserted in this code? As per my understanding it will asset CS only when there is a write operation, please correct me if I’m wrong.
Thanks,
Varun

[@RohitThakur-rs5li]

Sir can you provide me the link for this spi code single master with multiple or single slave and its test bench too.
Thanks in advance

[@srivanigara434]

where can we find state machine figure for this program??

[@naveenbodige4685]

sir can you please send the simple verilog code for SPI..just for simulation not for implementation

[@gtcollection6933]

github.com/nandland/spi-master/tree/master/Verilog

[@richadjackson3617]

How i get knowledge on ATPG ??

[@naveenbodige4685]

how to write for multi slave