SPI Master in FPGA, Verilog Code Example

[@shaneliu7512]

It's really hard to find hardware tutorial, there should be more hardware content in the world.

[@MrKaizen75]

Check out Vipin Kizheppatt's channel

[@rahmatdwiputra]

Thanks!! the world is in need of more fpga content!!

[@vahanabrahamyann]

I think its not good idea to use registers like SPI clock.

[@recurentgamer1142]

Thanks for the tutorial, but I think it would be nice to put an IP-core visual representation of this SPI, i.e. box with all i/o, etc listed within the code.. Should it be 2 SPI modules? Data comes from a source to TX on Master, then Master transfers it via MOSI to Slave?

[@ngocmanprocoder]

Hi, i have a question, and i need your assistance. In a system, we make transfer with single port sram through spi protocol instead of transfering directly. Why? Many thánks

[@sumitpahuja2858]

I am unable to simulate this code xilinx ise 14.7. please suggest me another one

[@fmm5322]

I want to ask another question. How to read the contents of the register in verilog through spi. We knoww the addrsss of the first register. Then the address auto inreements

[@ayyappana9101]

Hi ! Can you suggest how to interface spi flash with spartan 6 to write and read user data

[@mrrtommyversace3618]

Hello.
Greate video, thx for your work!

[@naveenbodige4685]

can you send the simple verilog code for SPI

[@ravindrabisram137]

In case you haven't gotten it yet, its on GitHub.
github.com/nandland/spi-master/blob/master/

[@RenegadeFury]

Thanks for making this video, at 5:55,
why does there need to be an extra delay for the output spi clock? Is it because you are using one cycle to copy the data on the input?
also does the half bits per clock really need to be 2 or more? It seems like it would work with a value of 1 from looking at this
EDIT: I see the need for delay for the output spi clk, it's because you are basing the output of the spi_clk on r_leadingedge which is already a cycle behind

[@fmm5322]

Please answer my question. U seem the most relevant

[@MrRamsampath]

Can you please share the specs which you referred for developing code?

[@fmm5322]

Whats the purpose of " r_SPI_Clk_Edges" in the context of spi mode and no of bits to transfer in that SPI transaction

[@jcudia9485]

watch the video🤣

[@monfry2675]

God bless you !

[@smilingthogth779]

Hello sir, how can get this verilog code?

[@junpenglu6627]

Thanks for the video! I have a question on how we should utilize or modify this code if we need to transmit and receive data 2 bytes at a time instead of 1 byte at a time as shown in the code?

[@ravindrabisram137]

I also have this question

[@fmm5322]

Make clock edges from 16 to 32 with counters updated from 3 bit to 4 bit

[@StrsAmbrg]

What is the programming language you are using? Look like Pascal, but is not.

[@fmm5322]

Two very basic questions
1. In MISO always block why you need to check the (o_tx_ready) signal.??? 🤔. o_tx_ready is the flag generated by the spi master to tell the upper module that its ready for next transmission on MOSI..
2. In first always block where we are counting the edges of the master clock (i_clk) to generate the spi clock edges.. Kindly elaborate who the trailing and leading edges are correlated with this count?

[@fmm5322]

Anyone please

[@egegoksu9557]

Hey, have you found an answer for 1st question?

[@fmm5322]

Nope.

[@Ravikumar-kb8fn]

How to convert SPI to I2C protocols using Verilog Code??

[@hanbyeolkwon559]

Thanks for really helpful video. But I have a question that how to make and send 'real' signal in FPGA. I mean, if I want to SS low at specific time how to do it?? not for testbench.

[@Nandland]

The only source of truth is your clock. Time does not exist to an FPGA. Only clock pulses. So you need to 1. Know the clock frequency. 2. Count clock pulses. That's how you know anything at all about time.

[@hanbyeolkwon559]

Maybe what I have to do is make counter and signal in the top module. It would be harder than I thought.... but thank you for your answer!

[@geoshah]

What's the function of the code
reg [2:0] SCKr; always @(posedge clk) SCKr

[@Nandland]

Creates a shift-register.

[@fmm5322]

@@Nandland answer my questions please

[@qigao5458]

I feel so hard, what ability do I need to understand?

[@mo938]

Practice. Never give up.

[@SiavashRaveh]

Hi, you have sold this tutorial on udemy

[@ajtechnologies4185]

$CLOG2 is giving error in synth

[@Nandland]

What's the error? I suggest posting your full question and the error to stackoverflow.com.

[@ajtechnologies4185]

@@Nandland ERROR:HDLCompilers:26 - "Code.v" line 60 unexpected token: '$clog2'
ERROR:HDLCompilers:26 - "Code.v" line 60 expecting ':', found ')'
that is line 60 of your github code.

[@unfrostedpoptart]

@@ajtechnologies4185 $clog2 has been around since Verilog2005 and in SystemVerilog. What synthesis tool are you using? How old is it?

[@marrytran7703]

@@unfrostedpoptart Hi David, I also have the same error like this when using Xilinx Tool: ISE-Design Suite 14.7. I haven't fixed it yet, Could you help me suggest the solution for that error? Thank you so much.

[@Basti1987chiller]

can we please all come to the conclusion that the programming language we use is C