@@sritech20 I worked for Morgan Ceramics/ Advanced Materials, facility in U.S. is now closed after being bought out by a competitor. I am currently enjoying retirement.......
@@sritech20 I was a Process Engineer as well, supporting 3 class 1000 clean rooms as well as our facilities Fine Pitch Dicing Champion. I also designed and produced customer samples and prototypes.
The bumping process mentioned here is C4 bump, used to bump flip chips, there is a "micro C4" or "micro bump" process, which replaces stencil printing of solder paste by lithography and ECD plating process. micro C4, literarily achieves smaller bump diameter and bump gap/height, close to the range of Cu pillar.
Sorry. I missed this question. Wafer bumping with printing was used long time ago so I am not sure which company still provide this service. And wafer bumping is done for wafer, round shape.
Sometimes solder is made on package substrate pad so called Solder on Pad(SoP). Cu pillar bump without solder cap is also available for some high performance computing applications. But solder bump on wafer is much popular solution.
Thanks for asking. I don't know about good reference book so I attach some links for reference material. www.dfrsolutions.com/hubfs/Resources/services/Overview-of-Copper-Pillar-Technology.pdf smtnet.com/library/files/upload/Fine-Pitch-Micro-Bump-Cu-Pillar-and-BOT.pdf www.circuitnet.com/news/uploads/1/IMAPSDPC2010FCEMReliabilityCuP.pdf pdfs.semanticscholar.org/992d/7bf7dc7df4c58f35a9e35413a56452f6cce3.pdf
Sorry, this process flow is simplified one for introduction and does not include details. There are lots of options for seed layer in the plating solder bump and one popular composition is Cu and Ni is another one. Seed layer is for following solder electroplating process. UBM is fabricated on top of die pad by sputtering process, physical vapor deposition which does not need electrode. Seed layer is fabricated on top of UBM by plating process, chemical deposition which needs electrode. So final stack-up will be die pad-UBM-Seed layer-Plating solder bump. These are only one of many options and others are available as well.
Similar but little bit different. RDL is redistribution layer and its simplified process flow is passivation layer coating & expose & develop --> Seed layer sputtering --> Photo Resist coating & expose & develop --> RDL electroplating --> Photo Resist strip --> Seed layer etching. I will make a video about WLCSP later.
시청해주셔서 감사합니다. 제가 자세한 설명을 못드렸는데 두가지 모양은 Solder가 올라간 부분만 다른것이 아니라 Cu pillar가 Die pad와 접촉되는 밑에 부터 모양이 다른것입니다. 모양에 따라 Die pad 부분에 가해지는 Mechanical stress가 달라지고 이 Stess는 Die pad 아래에 있는 반도체 구조에 영향을 줍니다. 여러가지 의견이 있는데 일반적으로는 Cicle 형태가 Stress가 적어 Die pad 아래 구조를 손상시킬 확률이 적어 대부분 사용되고 있습니다.
![[Eng Sub] Flipchip die attach process: Bump, MR(Mass Reflow), TCNCP, LAB(Laser Assist Bond), NCP](http://i.ytimg.com/vi/Yr_1vcYdbvI/mqdefault.jpg)
Well done, thanks for the great video. I've worked in this industry for 20+ years, your presentation was outstanding!
Thanks and your kind compliment make me continue.
Its great to hear! where you working currently friend ?
@@sritech20 I worked for Morgan Ceramics/ Advanced Materials, facility in U.S. is now closed after being bought out by a competitor. I am currently enjoying retirement.......
@@johns4584 Its great pleasure to meet you here Mr.John. I'm a process engineer with nanotechnology from IN.
@@sritech20 I was a Process Engineer as well, supporting 3 class 1000 clean rooms as well as our facilities Fine Pitch Dicing Champion. I also designed and produced customer samples and prototypes.
Started working at bumping process and I am so lost… your video helped me to get some knowledge :) Thank you for sharing it 👍🏻👍🏻
솔더볼 개발경험자입니다.좋은 강의 감사드립니다
시청해주셔서 감사합니다. 저보다 전문가시네요.
Thank you. your explanation is very clear and helpful.
Thanks that was a super useful quick overview
Thanks for sharing! I’ll start a new project with bump process.
Thanks for watching. I wish you the best on your new project.
Very wellstructured presentation with lots of details. Thank you!
Thanks for watching and your kind comment.
The bumping process mentioned here is C4 bump, used to bump flip chips, there is a "micro C4" or "micro bump" process, which replaces stencil printing of solder paste by lithography and ECD plating process. micro C4, literarily achieves smaller bump diameter and bump gap/height, close to the range of Cu pillar.
Wonder if there are some ways to create the bumps on a 2mx2m area using a print technique (cheaper version)
Sorry. I missed this question. Wafer bumping with printing was used long time ago so I am not sure which company still provide this service. And wafer bumping is done for wafer, round shape.
Thanks for your knowledge sharing !
very well structured and presented !!!! helped me a lot
Thanks for watching and I am glad to hear about it.
Great video. After which stage or step of wafer manufacturing, wafer bumping is performed?
Wafer bumping is performed after all wafer manufacturing process are completed.
Wafer manufacturing (Fab) --> Wafer bumping --> Packaging (Assembly).
Would it be better to fab the solder bumps on packaging substrates instead of wafers?
Sometimes solder is made on package substrate pad so called Solder on Pad(SoP). Cu pillar bump without solder cap is also available for some high performance computing applications. But solder bump on wafer is much popular solution.
@@semicontalk3223 👍❤️
미국에서 크린룸 시공 업체를 운영하고 있는 유일한 한국인 회사 CleanRoomLogic 입니다. 반도체 크린룸 설계에 도움이 주셔서 감사합니다.
시청해주셔서 감사합니다. 도움이 되셨다니 저도 기쁩니다.
좋은 강의입니다.통화하고 싶습니다.
시청해주셔서 감사합니다.
very helpful sir thanks a lot
I can understand your accent dont worry good good
What is a good reference (review or book) that you recommend on failures and failure analysis of the copper pillars?
Thanks for asking.
I don't know about good reference book so I attach some links for reference material.
www.dfrsolutions.com/hubfs/Resources/services/Overview-of-Copper-Pillar-Technology.pdf
smtnet.com/library/files/upload/Fine-Pitch-Micro-Bump-Cu-Pillar-and-BOT.pdf
www.circuitnet.com/news/uploads/1/IMAPSDPC2010FCEMReliabilityCuP.pdf
pdfs.semanticscholar.org/992d/7bf7dc7df4c58f35a9e35413a56452f6cce3.pdf
we like to get some test samples. Wonder the contact information.
Unfortunately I don't have contact information.
This is great - thank you - Q: What is the composition of the seed layer in the plating process, and how is it different than the UBM?
Sorry, this process flow is simplified one for introduction and does not include details. There are lots of options for seed layer in the plating solder bump and one popular composition is Cu and Ni is another one. Seed layer is for following solder electroplating process.
UBM is fabricated on top of die pad by sputtering process, physical vapor deposition which does not need electrode.
Seed layer is fabricated on top of UBM by plating process, chemical deposition which needs electrode.
So final stack-up will be die pad-UBM-Seed layer-Plating solder bump. These are only one of many options and others are available as well.
Is RDL in the wafer level packaging created the same way?
Similar but little bit different. RDL is redistribution layer and its simplified process flow is passivation layer coating & expose & develop --> Seed layer sputtering --> Photo Resist coating & expose & develop --> RDL electroplating --> Photo Resist strip --> Seed layer etching. I will make a video about WLCSP later.
항상 감사합니다. 만드신 영상들 애청하고 있습니다. 3분11초에 Cu pillar 위에 Solder 올라간게 Circle 모양과 Oval 모양이 있다고 하셨는데, 각각의 특징이 있을까요? 가령 Circle과 Oval의 각 목적과 용도가 다를까요?
시청해주셔서 감사합니다. 제가 자세한 설명을 못드렸는데 두가지 모양은 Solder가 올라간 부분만 다른것이 아니라 Cu pillar가 Die pad와 접촉되는 밑에 부터 모양이 다른것입니다. 모양에 따라 Die pad 부분에 가해지는 Mechanical stress가 달라지고 이 Stess는 Die pad 아래에 있는 반도체 구조에 영향을 줍니다. 여러가지 의견이 있는데 일반적으로는 Cicle 형태가 Stress가 적어 Die pad 아래 구조를 손상시킬 확률이 적어 대부분 사용되고 있습니다.