GMT20250121 211301 Recording 2880x1800

This is the Official Presentation on the Mirabilis Design VisualSim solution for the entire Automotive Industry. This presentation covers network, ECU, software and semiconductor exploration. It covers the needs for car OEMs, Tier One Suppliers and Semiconductor vendors.
1. Network modeling including multi-protocol (CAN+TSN) topology, multi-agent per node traffic, capacity planning, routing, ECU placement and mapping signals to ECU
2. Software mapping, partitioning (HW and SW), distribution across multi-ECU, processors and cores, cache coherency
3. Semiconductor exploration of chiplets, HPC and GPU
4. Power distribution, consumption, management and thermal effects
Estimating latency and power for different use-cases in full ve, ECU and Networks
Overview: This session will focus on a common system-level simulation platform that can be shared by Semiconductor companies, Tier One Suppliers, OEMs in designing the entire E/E architecture. The transition to everything digital and electronics is causing a number of design challenges across the ECU, processors, semiconductors, software and networks. Current systems engineering solutions are focused on the correctness of algorithms, requirements management and SysML behavior model. What is required is accurate latency, throughput, buffer occupancy, optimal scheduling and power consumption measurement, prior to development.
We will delve into the design challenges associated with the new generation automotive system design, changes in the power efficiency and latency requirements, and handling of Distributed, Zonal, and Centralized Architecture computational. We show examples with use cases that originate at the SysML and refine all the way to micro-architecture. The examples will showcase the comparison and results for different use cases, topology, different SoC architectures, hardware modeling abstraction, software task graphs and traffic workload. We will look at applications such as braking, lighting, comfort, ADAS, EV, battery and safety system.
Key Takeaways:
1. E/E Architecture Evolution:
o Comparing the cost, performance and power consumed by the same use cases on Distributed, Zonal and Centralised architectures.
o Methodology to trade-off software complexity with compute resources, scheduling, multi-core distribution and network architecture
o Integrating legacy systems and meeting-bandwidth, low-latency communication.
2. Systems and Semiconductors Exploration
o Select the hardware, network and software to meet the requirements
o Optimize the system and semiconductor definition to share with OEMs and semiconductor suppliers
o Detect system bottlenecks, latency and power consumption for different use cases
3. Identify System Bottlenecks prior to Integration:
o Evaluate responses to failures and validate ISO 26262 and SOTIF requirements.
o Trade-off between latency, power consumption, and computational efficiency.
o Optimal task mapping and resource allocation in multi-core processor systems.
4. Role of VisualSim in Architecture Design:
o Learn how VisualSim system-level IPs accelerate model construction and enable rapid architecture trade-offs.
o The methodology to debug system behaviors and failures
o Regression simulation to identify and optimize the system specification
5. Case Studies and Real-World Applications:
o Examples of how VisualSim has been used to model different use cases on the hardware, software, OS and network to optimize automotive E/E systems.
o Insights into achieving significant reductions in latency and power through architectural refinements.
6. Future Trends in E/E Architectures:
o The impact of emerging technologies such as AI-driven optimizations and multi-core ECUs.
o Advancements in centralized architecture to increase modularity and scalability.