I have an ESP32-C3 which has a single Risc-V and an ultra-low-power co-processor... but imagine the process is the same as the ESP32-S series (which has 2 Xtensa LX6 high-performance cores as well as a ULP co-processor) But assuming I can compile 8KB ULP code and flash (0x50000000).. in addition to the RiscV code (0x10000), does the inter-core communication work the same? For example, I imagine that they can each access peripherals (ex. !UART) so they need to coordinate via some shared ram?
The "loop" is yet another task. that runs on core 1 You leave it empty if not used/needed. Avid using core 0 for tasks if using wireless (which runs on core 0) or you will get weird wifi issues like crashes and disconnects.
Interesting! As usual!
I have an ESP32-C3 which has a single Risc-V and an ultra-low-power co-processor... but imagine the process is the same as the ESP32-S series (which has 2 Xtensa LX6 high-performance cores as well as a ULP co-processor)
But assuming I can compile 8KB ULP code and flash (0x50000000).. in addition to the RiscV code (0x10000), does the inter-core communication work the same? For example, I imagine that they can each access peripherals (ex. !UART) so they need to coordinate via some shared ram?
The "loop" is yet another task. that runs on core 1 You leave it empty if not used/needed. Avid using core 0 for tasks if using wireless (which runs on core 0) or you will get weird wifi issues like crashes and disconnects.