Synchronous Buck Converter

Поделиться
HTML-код
  • Опубликовано: 25 июн 2020
  • Learn practical design-oriented modeling and control of switching power converters using analytical and simulation tools in CU on Coursera's Averaged-Switch Modeling and Simulation course. Find out more at www.colorado.edu/oai/averaged....

Комментарии • 15

  • @jayc2570
    @jayc2570 5 месяцев назад

    Hey its my alma mater, fundamentals of power electronics class. Good to see Professor Maksimovic on RUclips! Thanks for posting these videos, its like being in class again.

  • @Lime3919
    @Lime3919 3 года назад +6

    Wow, someone just explained what I wanted to know. Now I just wish he explained the on and off cycles between Q1 and Q2.

  • @ionix2000
    @ionix2000 Год назад

    Finally, now this was explained exactly how I wanted. Thank you.

  • @FilipeSilva1
    @FilipeSilva1 3 года назад

    Perfect. Thank you.

  • @rubenayla
    @rubenayla 3 года назад

    Awesome. Very clear

  • @anjankrishna9775
    @anjankrishna9775 Год назад +1

    great explanation 👏

  • @jsurinderveygal561
    @jsurinderveygal561 3 года назад

    Thank you

  • @aakashsharma8084
    @aakashsharma8084 3 года назад +1

    yeah same here , got exactly what i wanted

  • @Honduras60
    @Honduras60 2 года назад +2

    Awesome video. Thanks. He mentioned that "obviously both switches would not on at the same time". But why is that? And what would happen if they were on at the same time?

    • @akhurash
      @akhurash 2 года назад

      If you had both turned ON at the same time, you would be shorting the input to ground.

  • @BradKwfc
    @BradKwfc Год назад

    Awesome video very well explained.
    I keep having buck converters fail. All are the same converter with the same components. From early looks its the same MOSFET that fails over and over again. If I were to guess I would guess it's Q2 because the inductor discharges at a faster rate than it charges so I'm seeing higher currents through Q2. Is my thinking right?

    • @brendankopf6249
      @brendankopf6249 Год назад

      Hi BradK. Your hypothesis may be correct, especially if you are using 2 different FETs with different Rds,on values. In addition, however, stray inductance due to FET package and layout in a discrete supply can cause negative voltage spikes on the gate of the low-side FET (Q2). This can violate the Vgs limit of Q2 if you are driving the gate really hard. If you find that this is the case, you can add a couple components to the gate of Q2 -- a low resistance series R for charging the gate and a Schottky diode for discharging the gate. Also, check for ringing on your switching node, as this can violate the Vds limit of Q2 if you did not consider it when selecting a FET for your low side. Hope this helps!

    • @BradKwfc
      @BradKwfc Год назад

      @@brendankopf6249 Awesome info. Thanks for the suggestions I really appreciate it!

  • @brianlloyd6707
    @brianlloyd6707 Год назад

    It's unfortunate that his microphone is in a blender