Hey its my alma mater, fundamentals of power electronics class. Good to see Professor Maksimovic on RUclips! Thanks for posting these videos, its like being in class again.
Doesn't the body Diode of Q1 interfere with the realization of the Switch? If IL is supposed to be sourced from Vg when Q1 is ON, shouldn't we prevent IL from flowing back to Vg when Q1 is OFF? Wouldn't an IGBT be more appropriate to realize Q1?
Awesome video. Thanks. He mentioned that "obviously both switches would not on at the same time". But why is that? And what would happen if they were on at the same time?
It's "obvious" from the schematic, because they are going exactly in anti-phase one to another i.e. they are inverted as of the schematic (one has a buffer the other one has an inverter, both are the same delay as buffer and inverter have almost same delay, so there is no asymmetric PWM fed into any of the two gates.) And don't listen to Indian explanations.
Hallo, ich möchte mein Buck Converter mit Matlab simulieren, aber ich habe bisher die PI Parameter genau nicht bestimmt. Kann jemand mir helfen um die Parameter zu bestimmen.
Awesome video very well explained. I keep having buck converters fail. All are the same converter with the same components. From early looks its the same MOSFET that fails over and over again. If I were to guess I would guess it's Q2 because the inductor discharges at a faster rate than it charges so I'm seeing higher currents through Q2. Is my thinking right?
Hi BradK. Your hypothesis may be correct, especially if you are using 2 different FETs with different Rds,on values. In addition, however, stray inductance due to FET package and layout in a discrete supply can cause negative voltage spikes on the gate of the low-side FET (Q2). This can violate the Vgs limit of Q2 if you are driving the gate really hard. If you find that this is the case, you can add a couple components to the gate of Q2 -- a low resistance series R for charging the gate and a Schottky diode for discharging the gate. Also, check for ringing on your switching node, as this can violate the Vds limit of Q2 if you did not consider it when selecting a FET for your low side. Hope this helps!
Hey its my alma mater, fundamentals of power electronics class. Good to see Professor Maksimovic on RUclips! Thanks for posting these videos, its like being in class again.
Wow, someone just explained what I wanted to know. Now I just wish he explained the on and off cycles between Q1 and Q2.
Finally, now this was explained exactly how I wanted. Thank you.
great explanation 👏
Doesn't the body Diode of Q1 interfere with the realization of the Switch? If IL is supposed to be sourced from Vg when Q1 is ON, shouldn't we prevent IL from flowing back to Vg when Q1 is OFF? Wouldn't an IGBT be more appropriate to realize Q1?
Awesome video. Thanks. He mentioned that "obviously both switches would not on at the same time". But why is that? And what would happen if they were on at the same time?
If you had both turned ON at the same time, you would be shorting the input to ground.
It's "obvious" from the schematic, because they are going exactly in anti-phase one to another i.e. they are inverted as of the schematic (one has a buffer the other one has an inverter, both are the same delay as buffer and inverter have almost same delay, so there is no asymmetric PWM fed into any of the two gates.)
And don't listen to Indian explanations.
@@akhurash yes, the thing is they cannot be both turned on by design. they are exactly in anti-phase given the circuit represented in the video.
Hallo, ich möchte mein Buck Converter mit Matlab simulieren, aber ich habe bisher die PI Parameter genau nicht bestimmt. Kann jemand mir helfen um die Parameter zu bestimmen.
Awesome video very well explained.
I keep having buck converters fail. All are the same converter with the same components. From early looks its the same MOSFET that fails over and over again. If I were to guess I would guess it's Q2 because the inductor discharges at a faster rate than it charges so I'm seeing higher currents through Q2. Is my thinking right?
Hi BradK. Your hypothesis may be correct, especially if you are using 2 different FETs with different Rds,on values. In addition, however, stray inductance due to FET package and layout in a discrete supply can cause negative voltage spikes on the gate of the low-side FET (Q2). This can violate the Vgs limit of Q2 if you are driving the gate really hard. If you find that this is the case, you can add a couple components to the gate of Q2 -- a low resistance series R for charging the gate and a Schottky diode for discharging the gate. Also, check for ringing on your switching node, as this can violate the Vds limit of Q2 if you did not consider it when selecting a FET for your low side. Hope this helps!
@@brendankopf6249 Awesome info. Thanks for the suggestions I really appreciate it!
Awesome. Very clear
Perfect. Thank you.
yeah same here , got exactly what i wanted
Thank you
It's unfortunate that his microphone is in a blender