Thank you Zach and Altuim Academy for another brilliant deep dive topic. I use stitching via's in my design for ground returns and tying ground layers etc. I never took into consideration the spacing shielding properties and would play around with the spacing not understanding exactly how and why, apart from reducing impedance. Until now that was the extent of my knowledge on how to use stitching via's. 🙌👍
When adding gng vias to connect all the planes, I usually set the opasity of the planes to 50 basically giving you a view through all the planes/layers, so you can easily see the areas where you can add gnd stitching vias without having to move a lot.
That's a good point, I normally do it with polygons after I have them drawn the way I like them. The automatic tool will apply clearance rules to the via array but if you're doing it by hand you can run into clearance errors, setting the opacity definitely helps.
To place additional vias and connect them properly you need of course copper from one layer to the other layer. To check this Altium Designer has a nice Design Rule. It is called ReturnPath and can be found in High Speed Section of your Design Rules.
As someone who's layed out a few pretty nice EVBs for sub 6Ghz RF products my main goal was always best return loss for my traces. Proper via spacing is very important when thinking of cpwg. When meeting a trace and SMA it's a pretty big challenge (no sharp corners, tear dropping preferred). VIA spacing is critical and also artwork on transitions from a trace to any other shape is almost as critical. When in doubt always talk to your fabricator. Loving these vids.
You should see the video I did on digital signals through a coplanar waveguide, the via pitch and the distance via-to-trace clearance both have a big effect on bandwidth.
Btw, doing the routing of hi-speed-signals (including I/Os with considerable short rise/fall times) early and placing the return vias at the same time when they swith layers can reduce later problems/overhead-work to add the return vias.
Yeah I would agree to try and place that when routing just those signals, but sometimes you need to re-route... it would be nice to have a design rule that allows checking for a stitching via based on net class.
Hello Zach, thanks for the nice video! It would also be great to make it possible to check for the presence of stitching vias by Altiums DRC. I think the idea pitch already exists in bugcrunch for a long time. Probably needs a little push by an expert like you. :)
I recently talked with someone about this and they are playing with the idea of adding stitching vias and antipads automatically around specific signal vias, we'll see if the feature ever goes live. I do not think I am the first person to have requested this.
I'd love some info on via fill % during enig/ hasl. I'm using stitching vias for thermal conductivity, and not sure on optimal size / qty to get best bang for buck, from standard via plating processes without extra fill complexity.
Unless you use very small via-holes (and or Micro-Vias / buried) the dimensions and amount of stitching vias for thermal puposes will not alter the production costs significantly i guess. We'll see what Zach has to say.
Given the finite hole-wall to hole-wall clearance limits for mechanical drilling, I think you would get the best bang for your buck with some intermediate value for the via size. That's just my intuition based on drill cost and the heat flux you would want to achieve across the board. It's actually a fun little dual optimization problem, maybe I'll play with it and if it's fruitful I'll do a video on it.
Great video! Thank you very much.. I always used the vías super close one to the next one.. being so conservative has any inconvenience? On the other hand, why you use 2 when the DK is 4? Thanks!
I used Dk 4, the refractive index is equal to 2 if Dk is 4, that value (square root of Dk) is what determines the propagation velocity. Being conservative and using the vias super close to each other is fine but might add cost per drill hit at volume manufacturing. The cost per drill hit is small and is normally ignored in prototypes, but it adds up in volume production. There is also hole-to-hole clearance requirement that has to be satisfied.
I still don't understand, why you have placed so many vias, which can shield up to 37 GHz signal, while the actual signal is only 2.4 GHz and it's also not explained, why there are 2 rows of them.
I have a question about placing vias near low speed digital traces. You mentioned its necessary to "maintain a return path when crossing multiple layers" I don't fully understand. Wouldn't the return current flow from the GND connection on whatever SPI IC the connections lead to? Why do you need it near the physical transition? Could you explain the physics here a bit? Thank you so much! Very grateful for your videos.
Hi Ryan, yes the current ultimately reaches the GND pin on the IC, but between the TX and RX ICs the trace has some capacitance to ground, which means the current in the GND pin is the displacement current from that capacitance. If you make a transition through a via and do not provide nearby GND, you interrupt some of that displacement current flow by decreasing the capacitance between the signal conductor and the GND conductor. Without a via, that displacement current will be induced by fringing fields to any nearby conductors, so it becomes unclear where the displacement current exists. That means there will be higher radiation, and in the cases where the signal has very fast edge rate the radiation can be quite strong. In the case of differential pairs, we sometimes prefer stitching vias but not simply for providing a return current on a differential via transition; that's a topic for another video.
If you're already using a fence at 20 mils, why stitch at only 250 mil or 80 mil? Is it to make the design intent of the antenna feed stand out? Do the stitches, even when separated from traces, cause too much disruption to the planes? Do fab houses still charge per drill hit, even though that doesn't seem to show up in their online quotes? (Or do they if you stitch over most of the board?) Do they start charging at high volumes, so you want to avoid getting into the habit with prototypes?
I think there is a lot going on with stitching vias that has to be balanced. For example if you already have close stitching as a fence on specific lines and the board edge then you might not need it in the internal region of the board. For example, what if you have a power rail on an internal layer? Closely spaced stitching vias could turn that rail or plane into swiss cheese. Another reason for stitching could be to link all the copper together to help with heat transfer, then you want dense vias in the region where heat is being generated. In fabrication, you can get charged per drill hit as a function of drill diameter when you go to high volume due to tool consumption, but in small prototype batches they might not chare per drill hit as they can factor in enough margin to cover tooling cost.
Hi Zach, why do L2-L5 have a cut out below the antenna trace. Is it because the idea was to make the antenna trace thicker by distancing gnd further away in the stack and hence use L6 as a reference for the coplanar wave guide?
Two reasons: 1) It was used in the reference design, and to de-risk the design we used a line design that we know works, 2) it requires a wider width, which does give lower conductor loss. The nRF documentation makes some claim about reducing capacitance that would affect impedance or unintentional coupling to other traces, but that explanation is nonsense; you would actually want to keep the ground if that was your reasoning. In this design we kept everything (including digital) clear around the trace and we're not routing under it on an inner layer, so it will operate with low noise even with the ground clearance. In general, you do not have to do this. In some designs, it's better to keep all the ground because you actually need it. An example where I did this was in a radar board that we have in assembly. The board uses blind vias on the coplanar line and adjacent ground, but the layer stack has 10 layers total and tons of high speed digital, we have no choice but to route that digital stuff under L2 GND on internal layers because it has to connect to the radar SoC for configuration and data capture. If I were to eliminate ground in that design the board would definitely not work.
I say "must" with an asterisk. Fab houses like stackups that are symmetrical in terms of copper coverage, especially once you start going to higher volume. The main point they will worry about is warpage. If there is heavily uneven copper distribution on top and bottom half of the stack, there could be some warpage if one side of the stack cools before the other side after layer build up. The same could happen after repeated reflow. Since it's a simple design element that is easy to implement, most people just go for it. We've used uneven copper in small boards and have not had problems, even for a board going into order of 10k units production.
Can we integrate the following into this? As we know the stack up and the material properties loaded into the designer 1. Trace width calculator along with the impedance calculator 2. Via shielding of a net. (spacing calculated based on the stackup input) kindly let me know if it already exisits or if we need such a tool.
Thank you, the layer stack manager currently does not support coplanar waveguide with ground vias. The impedance and maximum TEM frequency will depend on the via pitch and spacing, so it is not a trivial problem to incorporate these features into the calculator. Other programs you can use to evaluate your coplanar waveguide design include Polar and Simbeor.
Hi, can you please explain to me one more time because I didn't get. Via shielding prevents frequencies which are lower or higher than a calculated frequency?
They help shield against all frequencies, but lower frequencies are much more effectively shielded than higher frequencies. The shielding is most effective against frequencies below some cutoff value. The cutoff is approximately determined by the distance between the vias, and when this distance is equal to a half-wavelength the frequency corresponding to that half-wavelength will be the highest frequency that is most effectively shielded without starting to strongly radiate.
And a 4mil annular ring ((18-10)/2)? Even for class II most PCB fabs want a min of 5mil... one thing to note is calling out finished hole size. So for a 10mil finished on an 18mil pad, they'd prob. be drilling 12 over that for the plating.
I've never had a Class II called out as must-be 5 mils with the two main fabs I use, as well as by my EMS clients. But there is one fab I have used that always requests teardrops added in Class II just for extra protection at the trace-to-pad connection, they do the same for Class III.
What do you mean by multiple substrates? Do you mean stacks of prepreg with different dielectric constants? In this case you have an effective dielectric constant that depends on the thickness of those stacked sheets, the simplest approximation is to use a thickness-weighted average to approximately get an effective dielectric constant. From this you could then calculate the wave speed in the substrate, and then you can estimate the spacing required for stitching to ensure isolation.
Because I was calculating the speed of electromagentic wave propagation in MKS units. The speed of wave propagation is the speed of light in vacuum (3e8 m/s) divided by refractive index, or square root of Dk (2).
Typically there are two situations where you need some kind of length matching in an RF system: when you are using differential RF components (some amplifiers do this) or if you have two lines and you need to precisely control the phase between the signals on those lines. Which type of instance are you referring to?
It is, just using some default settings you will provide some small additional shielding effectiveness around the low speed lines. Might as well not worry about it. However, with EMI susceptibility, may there is some situation where the via fence helps on a low speed line. However there are other methods that help with EMC once the design is complete, doing a respin just to apply via fencing to try and solve an EMI susceptibility problem for a low speed line does not make sense.
Hey Zach, great video! I was just wondering: if I have mounting holes that will be connected to a metal enclosure via screw, and create a via fence along the edges that is tied to the chassis that acts as chassis ground, will the shielding effect work? Thanks again!
The shielding effect can work regardless of where the vias are placed, if you have a fence structure they can create a shielding effect in certain frequency ranges.
![Megan Thee Stallion - Neva Play (feat. RM) [Official Video]](http://i.ytimg.com/vi/TpYTyAaTRts/mqdefault.jpg)
Thank you Zach and Altuim Academy for another brilliant deep dive topic. I use stitching via's in my design for ground returns and tying ground layers etc. I never took into consideration the spacing shielding properties and would play around with the spacing not understanding exactly how and why, apart from reducing impedance.
Until now that was the extent of my knowledge on how to use stitching via's. 🙌👍
Thanks a lot ❤
When adding gng vias to connect all the planes, I usually set the opasity of the planes to 50 basically giving you a view through all the planes/layers, so you can easily see the areas where you can add gnd stitching vias without having to move a lot.
That's a good point, I normally do it with polygons after I have them drawn the way I like them. The automatic tool will apply clearance rules to the via array but if you're doing it by hand you can run into clearance errors, setting the opacity definitely helps.
To place additional vias and connect them properly you need of course copper from one layer to the other layer. To check this Altium Designer has a nice Design Rule. It is called ReturnPath and can be found in High Speed Section of your Design Rules.
Good point, I added a link to a Return Path rule video in the description
As someone who's layed out a few pretty nice EVBs for sub 6Ghz RF products my main goal was always best return loss for my traces. Proper via spacing is very important when thinking of cpwg. When meeting a trace and SMA it's a pretty big challenge (no sharp corners, tear dropping preferred). VIA spacing is critical and also artwork on transitions from a trace to any other shape is almost as critical. When in doubt always talk to your fabricator. Loving these vids.
You should see the video I did on digital signals through a coplanar waveguide, the via pitch and the distance via-to-trace clearance both have a big effect on bandwidth.
Thank you very much for this video, Zach! I get pleasure when watch such videos
Glad to hear that!
Btw, doing the routing of hi-speed-signals (including I/Os with considerable short rise/fall times) early and placing the return vias at the same time when they swith layers can reduce later problems/overhead-work to add the return vias.
Yeah I would agree to try and place that when routing just those signals, but sometimes you need to re-route... it would be nice to have a design rule that allows checking for a stitching via based on net class.
Hello Zach, thanks for the nice video! It would also be great to make it possible to check for the presence of stitching vias by Altiums DRC. I think the idea pitch already exists in bugcrunch for a long time. Probably needs a little push by an expert like you. :)
I recently talked with someone about this and they are playing with the idea of adding stitching vias and antipads automatically around specific signal vias, we'll see if the feature ever goes live. I do not think I am the first person to have requested this.
@@Zachariah-Peterson It sounds promising!
I'd love some info on via fill % during enig/ hasl.
I'm using stitching vias for thermal conductivity, and not sure on optimal size / qty to get best bang for buck, from standard via plating processes without extra fill complexity.
Unless you use very small via-holes (and or Micro-Vias / buried) the dimensions and amount of stitching vias for thermal puposes will not alter the production costs significantly i guess.
We'll see what Zach has to say.
Given the finite hole-wall to hole-wall clearance limits for mechanical drilling, I think you would get the best bang for your buck with some intermediate value for the via size. That's just my intuition based on drill cost and the heat flux you would want to achieve across the board. It's actually a fun little dual optimization problem, maybe I'll play with it and if it's fruitful I'll do a video on it.
Great video! Thank you very much.. I always used the vías super close one to the next one.. being so conservative has any inconvenience? On the other hand, why you use 2 when the DK is 4? Thanks!
I used Dk 4, the refractive index is equal to 2 if Dk is 4, that value (square root of Dk) is what determines the propagation velocity. Being conservative and using the vias super close to each other is fine but might add cost per drill hit at volume manufacturing. The cost per drill hit is small and is normally ignored in prototypes, but it adds up in volume production. There is also hole-to-hole clearance requirement that has to be satisfied.
Thanks for clearing out.@@Zachariah-Peterson
I still don't understand, why you have placed so many vias, which can shield up to 37 GHz signal, while the actual signal is only 2.4 GHz and it's also not explained, why there are 2 rows of them.
The via shielding(top to second layer) for micro strip line, when the via is connection on top layer it is not working. Why?
I have a question about placing vias near low speed digital traces. You mentioned its necessary to "maintain a return path when crossing multiple layers"
I don't fully understand. Wouldn't the return current flow from the GND connection on whatever SPI IC the connections lead to? Why do you need it near the physical transition? Could you explain the physics here a bit? Thank you so much!
Very grateful for your videos.
Hi Ryan, yes the current ultimately reaches the GND pin on the IC, but between the TX and RX ICs the trace has some capacitance to ground, which means the current in the GND pin is the displacement current from that capacitance. If you make a transition through a via and do not provide nearby GND, you interrupt some of that displacement current flow by decreasing the capacitance between the signal conductor and the GND conductor. Without a via, that displacement current will be induced by fringing fields to any nearby conductors, so it becomes unclear where the displacement current exists. That means there will be higher radiation, and in the cases where the signal has very fast edge rate the radiation can be quite strong. In the case of differential pairs, we sometimes prefer stitching vias but not simply for providing a return current on a differential via transition; that's a topic for another video.
If you're already using a fence at 20 mils, why stitch at only 250 mil or 80 mil? Is it to make the design intent of the antenna feed stand out? Do the stitches, even when separated from traces, cause too much disruption to the planes? Do fab houses still charge per drill hit, even though that doesn't seem to show up in their online quotes? (Or do they if you stitch over most of the board?) Do they start charging at high volumes, so you want to avoid getting into the habit with prototypes?
I think there is a lot going on with stitching vias that has to be balanced. For example if you already have close stitching as a fence on specific lines and the board edge then you might not need it in the internal region of the board. For example, what if you have a power rail on an internal layer? Closely spaced stitching vias could turn that rail or plane into swiss cheese. Another reason for stitching could be to link all the copper together to help with heat transfer, then you want dense vias in the region where heat is being generated. In fabrication, you can get charged per drill hit as a function of drill diameter when you go to high volume due to tool consumption, but in small prototype batches they might not chare per drill hit as they can factor in enough margin to cover tooling cost.
Hi Zach, why do L2-L5 have a cut out below the antenna trace. Is it because the idea was to make the antenna trace thicker by distancing gnd further away in the stack and hence use L6 as a reference for the coplanar wave guide?
Two reasons: 1) It was used in the reference design, and to de-risk the design we used a line design that we know works, 2) it requires a wider width, which does give lower conductor loss. The nRF documentation makes some claim about reducing capacitance that would affect impedance or unintentional coupling to other traces, but that explanation is nonsense; you would actually want to keep the ground if that was your reasoning. In this design we kept everything (including digital) clear around the trace and we're not routing under it on an inner layer, so it will operate with low noise even with the ground clearance. In general, you do not have to do this. In some designs, it's better to keep all the ground because you actually need it. An example where I did this was in a radar board that we have in assembly. The board uses blind vias on the coplanar line and adjacent ground, but the layer stack has 10 layers total and tons of high speed digital, we have no choice but to route that digital stuff under L2 GND on internal layers because it has to connect to the radar SoC for configuration and data capture. If I were to eliminate ground in that design the board would definitely not work.
Why *must* layers 4-6 be symmetrical with 1-3 in terms of copper fill? Is it just a convention? Does it stave off some manufacturing problems?
I say "must" with an asterisk. Fab houses like stackups that are symmetrical in terms of copper coverage, especially once you start going to higher volume. The main point they will worry about is warpage. If there is heavily uneven copper distribution on top and bottom half of the stack, there could be some warpage if one side of the stack cools before the other side after layer build up. The same could happen after repeated reflow. Since it's a simple design element that is easy to implement, most people just go for it. We've used uneven copper in small boards and have not had problems, even for a board going into order of 10k units production.
Can we integrate the following into this? As we know the stack up and the material properties loaded into the designer
1. Trace width calculator along with the impedance calculator
2. Via shielding of a net. (spacing calculated based on the stackup input)
kindly let me know if it already exisits or if we need such a tool.
Really Love these videos, they help me a ton!
Thank you, the layer stack manager currently does not support coplanar waveguide with ground vias. The impedance and maximum TEM frequency will depend on the via pitch and spacing, so it is not a trivial problem to incorporate these features into the calculator. Other programs you can use to evaluate your coplanar waveguide design include Polar and Simbeor.
Hi, can you please explain to me one more time because I didn't get. Via shielding prevents frequencies which are lower or higher than a calculated frequency?
They help shield against all frequencies, but lower frequencies are much more effectively shielded than higher frequencies. The shielding is most effective against frequencies below some cutoff value. The cutoff is approximately determined by the distance between the vias, and when this distance is equal to a half-wavelength the frequency corresponding to that half-wavelength will be the highest frequency that is most effectively shielded without starting to strongly radiate.
@@Zachariah-Peterson thank you very much
And a 4mil annular ring ((18-10)/2)? Even for class II most PCB fabs want a min of 5mil... one thing to note is calling out finished hole size. So for a 10mil finished on an 18mil pad, they'd prob. be drilling 12 over that for the plating.
I've never had a Class II called out as must-be 5 mils with the two main fabs I use, as well as by my EMS clients. But there is one fab I have used that always requests teardrops added in Class II just for extra protection at the trace-to-pad connection, they do the same for Class III.
what if my PCB contains multiple substrates how do i calculate my constant ?
What do you mean by multiple substrates? Do you mean stacks of prepreg with different dielectric constants? In this case you have an effective dielectric constant that depends on the thickness of those stacked sheets, the simplest approximation is to use a thickness-weighted average to approximately get an effective dielectric constant. From this you could then calculate the wave speed in the substrate, and then you can estimate the spacing required for stitching to ensure isolation.
@@Zachariah-Peterson its exactly what i meant thanks a lot !
hello, the dk for fr4 is 4.. then why did you divide 3e8 by 2?
Because I was calculating the speed of electromagentic wave propagation in MKS units. The speed of wave propagation is the speed of light in vacuum (3e8 m/s) divided by refractive index, or square root of Dk (2).
How to length match rf lines in pcb ..
Typically there are two situations where you need some kind of length matching in an RF system: when you are using differential RF components (some amplifiers do this) or if you have two lines and you need to precisely control the phase between the signals on those lines. Which type of instance are you referring to?
@@Zachariah-Peterson i have to match the phase of two signals
Is there any dimension for using accordion length tuning
Stitching via for low speed stuff look pretty useless...
It is, just using some default settings you will provide some small additional shielding effectiveness around the low speed lines. Might as well not worry about it. However, with EMI susceptibility, may there is some situation where the via fence helps on a low speed line. However there are other methods that help with EMC once the design is complete, doing a respin just to apply via fencing to try and solve an EMI susceptibility problem for a low speed line does not make sense.
Hey Zach, great video! I was just wondering: if I have mounting holes that will be connected to a metal enclosure via screw, and create a via fence along the edges that is tied to the chassis that acts as chassis ground, will the shielding effect work?
Thanks again!
The shielding effect can work regardless of where the vias are placed, if you have a fence structure they can create a shielding effect in certain frequency ranges.
@@Zachariah-Peterson thank you very much for this, Zach. Helps cleared out some of the doubts that I have. Thanks again! 😃🫡