How to make gm/id plot in Cadence Virtuoso ADE

[@ZzzJony]

点击运行，没有6:39处的result那个表，导致最后所有图表也都只有一条线，怎么回事

[@NTUchickEEn]

這影片幫大忙了 感謝

[@arfic14]

does the scs file used to save the parameters have an equivalent in synopsys hspice?

[@吳奕愷-m4i]

Thanks a lot. I have a question. I tried to make the gm/id * ft plot, just as you mentioned in the previous course. Yet the ft couldn't be simulated and drawn?

[@劉育任-f7b]

3:34分的Vd假設我是用180奈米1.8V的NMOS就是打0.9嗎？

[@live24win]

very nice and helpful video.

[@LeiJing-d5r]

泪目，终于搞懂了

[@彭浚佑]

請問要做PMOS的圖電路應該要怎麼接

[@看這個看這個]

受益良多，非常感謝!

[@邱柏縉]

你好~請問要怎麼叫出設計電路的畫面? 不好意思我是新手摸索不出來

[@xxggww8740]

How to make gm/id plot for stacked transistors in Cadence Virtuoso ADE? Thanks!

[@santhu475gangala6]

It's good to others if you provide English subtitles. Please can you forward the materials with me?
Thanks in advance

[@ericyeh3787]

I'll try it. I made a PMOS version in English for this topic. You are welcome to refer to this.
ruclips.net/video/D2DQzVb8rXU/видео.html

[@santhu475gangala6]

@@ericyeh3787 can you please provide folded cascode opamp by gm id technique in English.
Thanks

[@laiwu604]

老师，这里的VDS是依据什么设置的

[@宫坂家的永远]

感谢🙏

[@noeyedeer725]

非常感謝！

[@kevinpan7133]

勾选了saving DC operation point好像还是显示没有OS parameter，不知道是不是cadence出了问题。。

[@kevinpan7133]

解决了，是库的问题，换成65nm的库就没问题了

[@张开-m5y]

我也遇到了这个问题，不知道怎么解决

[@劉承儒-y5l]

​@@张开-m5y 我也跑不出來...應該也不是庫的問題，有確認選到對的

[@pdd1611]

为什么没有更新了呀

[@yksh3333]

感谢！

[@denebvegaaltair1146]

我点进来的时候真tm没想到会是中文 D:

[@jerryhuang568]

確實

[@ZzzJony]

点击运行，没有6:39处的result那个表，导致最后所有图表也都只有一条线，怎么回事