create_clock - SDC constraint, What, Why and How?

[@ManojKumar-ti7kn]

What tool do you use for waveform generation?

[@saikirangurugubelli7969]

What type of constraint is create_clock.? Design constraint or optimization constraints!?

[@nshuang1009]

It seems the clock and dat of these FFs are in opposite position at page 1. Typically, CLK port is represented by the triangle with circle. Thank you

[@guillaume8437]

Same comment for the swap CLK/Data but the circle only means that you trig on falling edge while no circle you trig on rising edge...

[@nshuang1009]

Thank you