Power Delivery Network Simulation Deep Dive - Part One
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- Опубликовано: 9 июн 2024
- Simulating the impedance spectrum is a crucial step in Power Integrity analysis. Often this includes a Power Delivery Network (PDN) Simulation. Today, Tech Consultant Zach Peterson begins a multipart analysis of PDN Simulation, including an overview, using SPICE in Altium Designer, field solvers, and more.
0:00 Intro
0:36 The PDN Analyzer
1:54 Field Solvers
2:45 SPICE Simulation
4:41 PDN Simulation Overview
11:25 A Sample Simulation in Altium Designer
For more Power Integrity videos, click here: • Power Integrity
For more Power Delivery Network (PDN) Simulation Deep Dive videos, click here: • Power Delivery Network...
For more PCB Design for Intermediate Users videos, click here: • PCB Design for Interme...
For more Tech Consultant Zach Peterson videos, click here: • Technical Consultant Z...
👉 PDN Impedance Simulation and Analysis in SPICE: resources.altium.com/p/pdn-im...
👉 Identifying Near-field EMI in a PCB's Power Distribution Network: resources.altium.com/p/identi...
👉 What Target Impedance Should You Use in Your PDN?: resources.altium.com/p/what-t...
👉 What is Spreading Inductance?: resources.altium.com/p/what-s...
👉 When Do PCB Power Plane Resonances Occur?: resources.altium.com/p/when-d...
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Great video!
Thanks for the videos Zach. Looking forward to the deeper dive into the available tools. Hopefully the upcoming Altair PollEx extension will be a viable option.
I'm working on a license at the moment... I'm definitely going to continue this whole thing with the new EMIStream extension!
Great video Zach! Looking forward to part 2! Of course my next question is how to validate the effectiveness of the PDN on a real PCB without $100,000 of hardware :-). Possible with a nanoVNA? I’ve been wanting to try that out and just haven’t gotten the time to fool around with it.
I have a LibreVNA that goes out to I think 6 GHz, maybe we will do exactly that with our 4-layer board. There is also the new EMIStream extension in Altium Designer that lets you do some PDN and EMI analysis, I'm going to show a tutorial with that coming up when we discuss power plane resonances.
Zach,
I love your presentations on this subject. My knowledge on this topic has been greatly increased. Thank You.
This brings up a point about distributed plane capacitance. Something I learned from Lee Richey is as inductance goes up capacitance goes down and the reverse. Since the formula ((DK*Length*width*farads constant)/ thickness) would it be cheaper to add two more layers to your stack up SGPPGS with thinner cores and prepregs between the P and G players, rather adding so many caps throughout the design? I know you have to consider using 2 ply materials for >5v higher voltages difference and then more distributive caps are required when this situation comes into play.
The cost of capacitive components, insertion, solder paste, surface area, and inspection are greatly reduced. Even return paths and EMI are greatly reduced. I have found the board cost only goes up by 10% to 15% on high volume boards and this cost can be much less than that of using parts to increase the distributed plane capacitance. The amount of capacitance really depends on the size of the board and the dielectric thickness of the material used. The DK value is not as important except for the plane impedance gets lower thus reducing the inductance the gets the more capacitance you will get.
I use SATURN PCBTOOL Kit for my designs at the frontend to see if this is a benefit and it also aids in the selection of the materials for my stack up. I have found that at least reduces the number caps in the design even on smaller boards. I would really appreciate your thoughts on this conceptual approach.
Thanks
Keep up the great work I really enjoy your talks.
Hey Bob,
Thanks for watching and I'm glad to hear this is all useful. You're right that adding another PWR/GND pair is also effective, and it could be more effective than just taking an existing decoupling network and doubling the number of caps, especially when you look at the higher freuqency range. You're basically putting another big plane capacitor in parallel. That also does reduce the inductance, or at minimum doesn't increase it assuming the spreading inductances are the same in these overlapping plane layers. At some point, adding more caps stops providing additioanl benefit because you're already well below target impedance values in the mid frequency range and you've totally eliminated any poles in the impedance spectrum, so you're right you only need so many caps. That being said, once you get to the mid-to-high frequency range (around 500 MHz to 1 GHz), doubling the plane capacitance probably is more effective than doubling the existing number of capacitors because the ESL value of those capacitors prevents them from further decoupling at those high frequencies. The other option is you go with really small case (0402 or 0201) MLCCs, which might also do the trick if you have even a small number of them. It depends on the exact frequency range and impedance reduction you need. Sometimes just adding a few bypass caps does the trick. But if you find you need an additional 20 MLCCs to get the impedance reduction you need near 1 GHz, and the additional plane gives you the same result, then why not go with the plane? It's all about looking at the impedance spectrum and determining the best course of action for your board.
@@Zachariah-Peterson I agree you have to address each design to the needs of the circuit now a days. I have been doing this 55 years and each of the thousand designs I have done are unique. Approaching each one with a view of what the puzzle really is, the more techniques and tools you have
, makes you a better designer. Lately I have been working with Gen Z 5 and CXL multi channel memory with 25 Ghz front end with many analog supplies for thee multiple voltages and custom chips and DRR5 memory. The main resolve is using skip vias to remove the stubs on the high speed buses and finding room for the returns path vias and still get the front to back traces short enough to minimize reflections on the daisey chained memory buses. The Z-axis differences even make it more difficult to match the lengths to get rid of the initial reflection spikes on the rising and falling edges. This has been the main issue to maintain the setup and hold time windows which are shrinking at each speed grade.
Great video! Thanks so much for breaking this down. One question though, what component from the Generic Simulation Components library did you use for Q1? I've got your same setup, but am having crazy swings and somewhere around 60(?!?!) amps for the drain current of Q1 (M1) for me. Much appreciated!
Hi Andy,
The component I used is MOSFET N-ch VDMOS. Just search that string inside the Generic Simulation Components library and it will come up. Note that this is a vertically-diffused power MOSFET model, so it's not the best representation of a CMOS logic circuit, but it can give the fast switching needed. If you want to get more accurate you could use one of the PMOS models and create a buffer, and then you could look at the output to see how noise propagates through to an IO. Again, not the most accurate as the best models are behavioral extractions from real components, but it's informative and I should probably do a video on it in the near future.
Also the rise time and voltage of the square wave source on the gate of Q1 are important. I used rise/fall time of 1 ns, and peak voltage of 1.2 V, that will certainly influence the total current driven through the FET.
@@Zachariah-Peterson Thank you for the quick reply! I'll give that component a try, much appreciated. Loving the videos, please keep them coming!
H Zach, in your simulation, how did you decide the the spreading inductance? I heard from Dr. Bogatin that there is no simple way to model, what we can do is field solver. And is spreading inductance asa the same as parasitic inductance? Or same as loop inductance? Hopefully you can hove one section to walk through inductance.
Hi Tim, you're right there is no closed form equation for the spreading inductance, you have to calculate it using a Green's function integral or using an infinite series of the structure's eigenfunctions. You can get an order of magnitude using the span across the vias, plane separation, and the distance between decouplers and input pins, but it's just an estimate. Also those vias need to be considered and it's usually best to put a bunch of them in parallel to connect to the die. To get an accurate spreading inductance value, you would need to use a field solver to solve Maxwell's equations directly, or you would use a numerical method for those integrals, brute force FEM would work. You can read more about it here: resources[dot]altium[dot]com/p/what-spreading-inductance
Hi Zach, there is a subject in power distribution network calculations that doesnt have a proper answer.
Most of the devices doesnt share power dissipation values, most likely only maximum or typical power consumption values.
How do you estimate power dissipation of a product as close as possible to the actual measurements?
Is it by gathering all the maximum power consumption values and dividing by square(2) to get RMS? or just gathering all the typical power consumption values?
This is a good question and I think there are several ways to approach it. Suppose you have a single processor and you want to estimate the total power consumption.
You can add up all the current for the interfaces you will use as well as quiescent values for the component, this multiplied by the supply voltage gives you a good order of magnitude estimate for the power dissipation.
You can also get an evaluation product for the component and measure the current being used during operation. When it is running your application you can determine the total power consumpion from the current measurement. If the design has multiple rails you can divide down the total current into each rail based on the current ratings for each regulator.
Neither approach is an exact science but at least it gives you a good order of magnitude estimate without building a complex test board.
@@Zachariah-Peterson
Thanks alot 😁
Great video! I remember using Spice Opus (similar to LTSpice and other) in college. These tools are great for simulating analog parts of circuits. However, it's tricky to simulate digital parts. It's hard to get digital models for IC's and if you want to create one, you have to be very careful how to setup the pins.
Thank you! You bring up a great point and that was why I used a really simple model to just simulate switching action, rather than looking at the effects on an entire set of logic circuits you'd find in a digital component. But you're right, if you want to get an idea of how the power bus noise transforms into I/O noise you would need a better model of the digital part.
If the tools available within Altium were as complicated as the menu system you'd be on to a winner. How about component parameters without clicking 'show more'? Every. Single. Time? We now export our designs using an old license to Orcad to use their built in PDN simulator. These things, like SI tools, sort the men from the boys. I've never got a spice design to work in Altium without large amounts of tweaking, sadly. Coming from Saber, Mentor Gfx and Hyperlinx, Altium has a very long way to go.
I'd take Altium over Mental Graphics any day of the week