Simulation, Synthesis and Design methodology in Verilog | #4 | Verilog in English

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  • Опубликовано: 18 сен 2024

Комментарии • 9

  • @vardayanishukla5178
    @vardayanishukla5178 2 года назад +1

    Thank you ma'am.You are a great Teacher.

  • @kcprincipaldrvilasnitnawar4628
    @kcprincipaldrvilasnitnawar4628 Год назад

    Nice way to teach HDL

  • @aneelakatlagunta8241
    @aneelakatlagunta8241 2 года назад

    Useful .... video 🥳

  • @yashtomar9899
    @yashtomar9899 3 года назад +2

    Can you please provide example for both methodology

    • @vlsipoint
      @vlsipoint  3 года назад +1

      For bottom-up 4 bit ripple carry counter and for top-down 4-bit parallel adder

  • @bhimashankarkattimani7074
    @bhimashankarkattimani7074 Год назад +1

    Am studying in 3rd engineering am thinking to learn verilog complete course. If i learn this completely wt package may i get in any SOFTWARE company l

  • @kumbhalakshmi1429
    @kumbhalakshmi1429 2 года назад +1

    madam,i completed my btech in electronics 2020,i attempted gate twice but even did not even qualified ,would i take vlsi training though i was not strong in fundmentals ?,can we belive in vlsi training and join in it for getting job in vlsi industry ?

  • @SNEHAKANDPAL-ev3np
    @SNEHAKANDPAL-ev3np 5 месяцев назад

    What is rtl?

  • @urbanunit-rg7bo
    @urbanunit-rg7bo Год назад

    viedo tu set kar kay chalayin

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