Just ran across this... But, in a very high-level sense, this sort of sounds similar to something like an 8080 or similar. Not much particularly useful to comment here (and not much immediate use-case for doing an 8-bit core). I had designed and implemented a CPU core in Verilog (with a custom ISA), but mine ended up very different (64-bit LIW/VLIW with 64 GPRs; no dedicated FPRs), and generally requires a bigger FPGA (a mostly feature-complete version fits into an XC7A100T). Previously, I had experimented smaller ISA's, but going smaller it is harder to make a case of "why not just use RISC-V?..." On a bigger FPGA, it is possible to get better performance-per-clock, by around 30% it seems, but this is harder to pull off within the limits of a smaller FPGA. Technically, my current core can also run RV64G (or, more correctly, RV64imfd; the A and Ziscr extensions are incomplete, but also not emitted by GCC). There are differences at the ISA level, but the design of the pipeline was such that most things be glossed over in the instruction decoder. System-level features differ a fair bit though (somewhat different interrupt-handling and MMU design). One drawback is that I am running my own OS (of sorts) on it, and debugging is a pain. Much more time spent debugging stuff than adding new features. Most recent things were things like an ELF-loader to allow running RV64 binaries in user-mode; and trying to debug the virtual memory system (to try to reduce the amount of crashing). For my own ISA, I have my own C compiler, and am using a modified version of PE/COFF for the binaries. Nothing intended for serious use, still mostly a hobby project at this stage.
Just ran across this...
But, in a very high-level sense, this sort of sounds similar to something like an 8080 or similar.
Not much particularly useful to comment here (and not much immediate use-case for doing an 8-bit core).
I had designed and implemented a CPU core in Verilog (with a custom ISA), but mine ended up very different (64-bit LIW/VLIW with 64 GPRs; no dedicated FPRs), and generally requires a bigger FPGA (a mostly feature-complete version fits into an XC7A100T). Previously, I had experimented smaller ISA's, but going smaller it is harder to make a case of "why not just use RISC-V?..." On a bigger FPGA, it is possible to get better performance-per-clock, by around 30% it seems, but this is harder to pull off within the limits of a smaller FPGA. Technically, my current core can also run RV64G (or, more correctly, RV64imfd; the A and Ziscr extensions are incomplete, but also not emitted by GCC). There are differences at the ISA level, but the design of the pipeline was such that most things be glossed over in the instruction decoder.
System-level features differ a fair bit though (somewhat different interrupt-handling and MMU design). One drawback is that I am running my own OS (of sorts) on it, and debugging is a pain. Much more time spent debugging stuff than adding new features. Most recent things were things like an ELF-loader to allow running RV64 binaries in user-mode; and trying to debug the virtual memory system (to try to reduce the amount of crashing). For my own ISA, I have my own C compiler, and am using a modified version of PE/COFF for the binaries.
Nothing intended for serious use, still mostly a hobby project at this stage.