SDC2020: CXL 1.1 Protocol Extensions: Review of the cache and memory protocols in CXL

The CXL interface adds both a memory and a caching protocol between a host CPU and a device. The Memory Protocol enables a device to expose memory region to the host to be used as system memory. The Caching Protocol can be used to directly cache host memory allowing devices to implement advanced flows like data prefetching and hardware atomics within a cache. Devices supporting both protocols can directly access the memory exposed to the host enabling high performance accelerator and computation storage use cases that are tightly coupled with the host CPU.
This presentation will review the cache hierarchy in a modern server CPU and review the memory and cache protocol flows used in CXL allowing a memory device and/or accelerator to directly participate in the cache hierarchy of the CPU.
Learning Objectives
Learn how CXL interface adds memory and caching protocol between a host CPU and a device.,Explore cache hierarchy in modern server CPU and share how memory and cache protocol is used in CXL to allow a memory device and/or accelerator to directly participate in the cache hierarchy of the CPU.,Demonstrate how CXL memory and cache protocols can directly access the memory exposed to the host enabling high performance accelerator and computation storage use cases that are tightly coupled with the host CPU.
Presented by
Robert Blankenship, Principal Engineer, Intel Corporation
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