really am very thankfull to u boss. Great explanation. i was struggled a lot with frequency divider , divide by 3 circuit. now your explanation made clear . thanks a lot sir.
Thanks a Lot sir ! I am a beginner in this topic and all I could find on the internet were stuff which never explained in layman's terms .I can proceed further thanks to ur brilliant explanation
Thank you for your helpful video. From 47:00 minutes onwards, you mentioned that capturing on the posedge of the clock will add another T to 1.5T. I believe adding a posedge FF will actually only add another T/2 and you will need another negedge FF to add another T/2 to produce the 2.5T ON.
or simply passing the data of negative edge flop again through negative edge triggered flop will produce overall 1s for2.5T and then orring all 3 will produce 50 %DC.
Excellent sir I have been struggling to understand this ...and finally today I understood because of u ...I have browsed and tried to study from everywer I could but I dint understand anything ua d best ...thank you so much......!!!☺😊 but I request you to ask the cameraman to shoot properly
OMG THANKS! You helped me cleared the concepts and this helped me a lot!! I've been trying to seek help but this has been far the greatest one i got. Keep making videos, ur a good teacher :D
Thanks kumar and please feel free to ask me any kind concepts related to digital design durga ganesh anyways my upcoming vedios are related to protocols like APB and ahb
Sir, I did not find your video on frequency divide by even numbers. Also it would be really very helpful if you could make a video on frequency divide by a fractional number e.g., .1.5, 4.5.
58:00 - isn't it unsafe to immediately delay by one whole clock cycle and OR the signals, isn't there a danger of sharp pulses at the output of the OR gate? Amazing work sir!
great explanation sir...from your side. Sir 50% duty cycle commonly knows. what about if they ask 33.33% and 80% duty cycle. Please give approach how it get it.
Sir, I did not find your video on frequency divide by even numbers. Also it would be really very helpful if you could make a video on frequency divide by a fractional number e.g., .1.5, 4.5.
Hi.. superb video to make things easy.. but coming to Mod-3 counter example, I think the LSB flop has to be negative edge triggered as well... only then count will be 00 in 1st clock cycle.. am i right or correct me if i went wrong...
Hi sir, I think preset and clear are active low signals it means they are active when preset=0 or clear =0, but @ 23 u are saying when clear =1 output= 0 how??
if ur working on physical design PNR ....could u please explain what is the best way to preapare clock tree specification file when a master clock and generates clock are provided
So an f/N (even) would just require a positive edge trigger flip for capturing the counter data and then Logical OR both of them right? Or is there any separate method for that?
For example for f/10 we just need a mod 9 counter and a Positive edge trigger flip flop to capture and give 1T extra portion of delay (same as how 0.5 delay is added to 4T for f/9)?
![Clock divided by 3 || Explained step by step! [Frequency divide by 3 ] F/3 or F/odd number](http://i.ytimg.com/vi/wxUqxSE_F5A/mqdefault.jpg)
![Clock divided by 3 || Explained step by step! [Frequency divide by 3 ] F/3 or F/odd number](/img/tr.png)
Best explanation ever! Logical and intuitive approach!
This video is the best for frequency dividers, no book can match your way of explaining stuff this easily .
Really
wow, wonderful explanation, clear cut concept understanding, amazing flow, and best content delivery, couldn't have learnt this topic any better
Mind-blowing Approach hats off Ganesh sir
It was soo good ...like now i have no confusion..such a great explanation...hats off
Excellent explanation. It has become so easy for us now. Thank you very much Sir.
46:51 ..was brilliant approach
really am very thankfull to u boss. Great explanation. i was struggled a lot with frequency divider , divide by 3 circuit. now your explanation made clear . thanks a lot sir.
you are the best clear concepts
very nice video to learn frequency divider circuits.....thank you
Very descriptive and nicely explained. I appreciate it. Thank you very much for sharing it.
Thanks a Lot sir ! I am a beginner in this topic and all I could find on the internet were stuff which never explained in layman's terms .I can proceed further thanks to ur brilliant explanation
Wonderful video. Very well explained
Best explanation. Basic totally cleared.
You actually make the impossible possible ..thank you very much 😄 if I hadn't come across this video I wuld break my head with this topic ..!!
Excellent and Very good video. I had a doubt but u solve it man. Thanks a lot.
Thank you for your helpful video. From 47:00 minutes onwards, you mentioned that capturing on the posedge of the clock will add another T to 1.5T. I believe adding a posedge FF will actually only add another T/2 and you will need another negedge FF to add another T/2 to produce the 2.5T ON.
I completely agree with this, I was also about to mention this.
It's a flipflop not a latch
or simply passing the data of negative edge flop again through negative edge triggered flop will produce overall 1s for2.5T and then orring all 3 will produce 50 %DC.
@@gauravkaushal7341 yes that's also a good and optimised way.
excellent approach and building the concept
Excellent sir I have been struggling to understand this ...and finally today I understood because of u ...I have browsed and tried to study from everywer I could but I dint understand anything ua d best ...thank you so much......!!!☺😊 but I request you to ask the cameraman to shoot properly
Excellent explanation sir
One of the best video I have seen 😊
I really love this video, it clearly demonstrate the frequency divider design method and way of thinking.
I understood this topic crystal clear. Thankyou!
Excellent explanation . Appreciate your efforts and time .
OMG THANKS! You helped me cleared the concepts and this helped me a lot!! I've been trying to seek help but this has been far the greatest one i got. Keep making videos, ur a good teacher :D
best lecture on frequency divider,thanq so much
very good explanation and learned a lot
Thanks kumar and please feel free to ask me any kind concepts related to digital design durga ganesh anyways my upcoming vedios are related to protocols like APB and ahb
please cover AXI lite protocol.. i am working on that therefore, need help..
Sir, I did not find your video on frequency divide by even numbers. Also it would be really very helpful if you could make a video on frequency divide by a fractional number e.g., .1.5, 4.5.
Really good way to approach the counters and frequency divider problems. :)
This is a very good video. Thanks! Please continue making videos =)
nice video, you had covered clearly and the explanation is good. The only thing that bothers is the noise through out the video. Great work..!!!
Sir i will check your upload videos in youtube is very less
Pleae upload more vodeos
Its very useful
Brilliant Explanation !!
Great video sir.
this content is so helpful...keep uploading more videos like that!!💜💜
good bro thanks for ur help
Thank you, ganesh sir. It was a nice explanation.
simply super sir...great explanation
best video Its worthy
simply amazing explanation
Best explanation
Thanks, very good explanation
Very good thanks a lot
thanks for such a nice explanation,please extend this video for designing for different duty cycles
Superb...thank you...that helped me a lot!!!!
Thanks for the explanation Sir, it is very helpful. But the cameraman is annoying. Looking forward for your protocol videos, please upload them quick.
58:00 - isn't it unsafe to immediately delay by one whole clock cycle and OR the signals, isn't there a danger of sharp pulses at the output of the OR gate?
Amazing work sir!
superb Explanation
Nice lecture thanq for uploading
great explanation sir...from your side. Sir 50% duty cycle commonly knows. what about if they ask 33.33% and 80% duty cycle. Please give approach how it get it.
Nice explanation. The cameraman should be more stable in cpturing the video.
you are awesome...Sir
👍Thank you sir
Thank you sir 💐❤️
Sir, I did not find your video on frequency divide by even numbers. Also it would be really very helpful if you could make a video on frequency divide by a fractional number e.g., .1.5, 4.5.
Very easy to understand.
nice stuff... Camera guy is really annoying...
Best ever!!
Hi.. superb video to make things easy.. but coming to Mod-3 counter example, I think the LSB flop has to be negative edge triggered as well... only then count will be 00 in 1st clock cycle.. am i right or correct me if i went wrong...
Does the circuit diagram of frequency divided by 10 will be the same as this mod 3 and mod 5 synchronous counter you have made
best video
sir can explain this in verilog , how to implement in code format
Thank you...This was helpful..
Hi sir,
I think preset and clear are active low signals it means they are active when preset=0 or clear =0, but @ 23 u are saying when clear =1 output= 0 how??
Can you please make an video for frequency divider for fractional number like 1.5,1.6, 2.5,4.5. etc
Can you please share some document or article or book that covers this topic? Thanks
Thank you very much .. Well Explained ! :-)
Flip flop will not make clock pulse delay, flip flop holds the value for one clock cycle
Good sir
The explanation seems to be good by is affected by the background noise and under expert cameraman.
if possible upload,how a flipflop and latch is detecting edge and level with basic gates...that i want sir
Thank U👍👍👌👌👌
There is a mistake at 47:00 it would be of 40% duty cycle...
how you got that sequence block for frequency divider....can you please explain?
very good explanation bro thank you. but noisy ambiance
hello sir,nice explaination.
how can v double the frequency i.e if input signal is 20 Mhz and v need an output signal of 40 Mhz.?
Use PLL
sir can u please upload the videos of frequenct divide by even number (synchronous and asynchronous)
Durga sir why did you stop making videos
from where i can read the stuff on fractional mod counter?
if ur working on physical design PNR ....could u please explain what is the best way to preapare clock tree specification file when a master clock and generates clock are provided
saivijayabhaskar.gade@gmail.com this is my mail id
could you please help me with 8/9 freq divider circuit ? I can't find such circuit .. thanks
sir how to slove for even numbers
Sir you explained nicely but cameraman is worst
Hi durga Ganesh
sir ,how to get output freq 2f/3 or 2f/5.pls explain.....!!!!!
just do f/5 by this method and later implement frequency multiplier ckt. You can google it
sir can u please upload the videos of basic FPGA CONCEPTS
So an f/N (even) would just require a positive edge trigger flip for capturing the counter data and then Logical OR both of them right? Or is there any separate method for that?
For example for f/10 we just need a mod 9 counter and a Positive edge trigger flip flop to capture and give 1T extra portion of delay (same as how 0.5 delay is added to 4T for f/9)?
tanq sir
no subtitle?
awesome lecture, but the worst camera work
thank you, cameraman, for yawning, I copied it instantaneously.