I was using 2N2222 or 2N3904 NPN transistors. Either of those will definitely work. BC547 is an NPN transistor that will probably work but I have not tested it myself.
BC547 work just as well but beware the leads are in a different order from 2N2222. With the flat part of the black plastic package facing you the pinout is, from left to right, CBE for the BC547 but EBC for the 2N2222. So you have to put them into the breadboard the other way round - flat side away from you, instead of facing you, as in these videos.
Hi thank you for this. Thank you. I hope you can add schematics. The circuit doesn't work on my end. Trying different resistors kinda works but ultimately the LED slowly starts to die out.
I do show the circuit level diagram for almost all the circuits I show. That is strange that it would die out. It sounds like a short circuit or bad transistor. Once it is latched the circuit should stay latched. I would say try again with a new breadboard and new transistors.
I still find it hard to imagine that we insert a flip-flop in every stage of a pipeline ( for each bit ). How much latency does it add? How is this never transparent? Isn’t there some fine tuning between these properties?
Yeah, it does seem a bit strange. ha ha With MOSFET's it is a slightly different logic gate configurations but the same idea. Ultimately what rate the processor can run is based on the switching time for the flip-flops or larger circuits to work at a given clock rate. The reason it works is that the switching time for each transistor is super fast. The GHz speed specification shown on processors is the clock rate. So depending on how many ring counter steps or program counter steps there are ultimately determines the latency of the computation. In some cases, it can add significant latency and computation time. It just depends on what type of program you are trying to run.
I am now building a binary counter, and I have a question about the SR latches built with logic gates. My understanding of SR latches is that there is an "invalid" state in which both inputs being high will result in both Q and Q' being low. However, I am finding that the only one I am able to build so far that includes this "invalid" state is the one constructed with NOR gates. When I use NOT and NAND gates, I do get a correctly functioning SR latches except when both inputs are high, both outputs are also high. Is this something to be concerned about?
That is a valid concern with the SR Latch. Having both the input and inverted input high can be an issue depending on how the circuit is used. If you are just looking at the output and you want it to be high in this case, it could work. The invalid state could also make it chance which value will be high or low. You might get the correct result but it was a 50/50 chance based on the tolerance of the parts if it will latch high or low. When building the binary counter the SR latch is actually a data flip-flop that has a wire going from the inverted output to the input. This makes it so there will not be an invalid state. You can also build the data flip flops with JK flip flops but that is not required for the binary counter. For the ring counter, it will be required to use JK flip flops.
I have a video on building a binary counter which is a shift register counter. In the 4-bit computer video there are two 7 stage ring counters which again are shift register counters. What application would you want to use the SISO for? I think building a serial-in parallel-out shift register would be interesting!
Applications: supply and receive the bits in serial MUL and DIV . Supply bits for old school sprites. We might want to skip this and rather have 15 colors plus transparency. The advantage I see is that the speed is the same for all sizes, while with SRAM or counters to select a bit we have fan out. Of course for a lot of real world applications parallel operation (CMOS IC) beats this anyway. I guess that every serial connection like twisted pair or an antenna is serial to parallel as soon as possible. Also ADC output is only serialised in audio applications!
I stumbled across your videos in an ad, and I had been looking for such a channel for a really long time now. Thank you🙏👍
Sure thing, I am glad you found it! Thanks for watching!
I welcome the return to the more sober presentation style.
Yeah, most of the videos try and present the information in a simple way!
Seek and you shall find
Excellent young man
Glad you found this helpful, thanks for watching!
Thanks for this explain what resistance you've been used ihave problem in resistor value
The red black red gold are 2K resistors, this is what is mostly used in the video.
SR as in set-reset, shown in the first demo with the 2 buttons
Yeah, that is correct.
Thanks, your's demonstration using Transistor is very good and easy for conception. (India)
Glad you liked it! Check out my latest video where I build a 4-bit computer using individual transistors.
are the transistors bc547?
I was using 2N2222 or 2N3904 NPN transistors. Either of those will definitely work. BC547 is an NPN transistor that will probably work but I have not tested it myself.
@@GlobalScienceNetwork thanks you
BC547 work just as well but beware the leads are in a different order from 2N2222. With the flat part of the black plastic package facing you the pinout is, from left to right, CBE for the BC547 but EBC for the 2N2222. So you have to put them into the breadboard the other way round - flat side away from you, instead of facing you, as in these videos.
Very useful information
Glad you liked it, thanks for watching!
Hi thank you for this.
Thank you.
I hope you can add schematics. The circuit doesn't work on my end. Trying different resistors kinda works but ultimately the LED slowly starts to die out.
I do show the circuit level diagram for almost all the circuits I show. That is strange that it would die out. It sounds like a short circuit or bad transistor. Once it is latched the circuit should stay latched. I would say try again with a new breadboard and new transistors.
I still find it hard to imagine that we insert a flip-flop in every stage of a pipeline ( for each bit ). How much latency does it add? How is this never transparent? Isn’t there some fine tuning between these properties?
Yeah, it does seem a bit strange. ha ha With MOSFET's it is a slightly different logic gate configurations but the same idea. Ultimately what rate the processor can run is based on the switching time for the flip-flops or larger circuits to work at a given clock rate. The reason it works is that the switching time for each transistor is super fast. The GHz speed specification shown on processors is the clock rate. So depending on how many ring counter steps or program counter steps there are ultimately determines the latency of the computation. In some cases, it can add significant latency and computation time. It just depends on what type of program you are trying to run.
I am now building a binary counter, and I have a question about the SR latches built with logic gates. My understanding of SR latches is that there is an "invalid" state in which both inputs being high will result in both Q and Q' being low. However, I am finding that the only one I am able to build so far that includes this "invalid" state is the one constructed with NOR gates. When I use NOT and NAND gates, I do get a correctly functioning SR latches except when both inputs are high, both outputs are also high. Is this something to be concerned about?
That is a valid concern with the SR Latch. Having both the input and inverted input high can be an issue depending on how the circuit is used. If you are just looking at the output and you want it to be high in this case, it could work. The invalid state could also make it chance which value will be high or low. You might get the correct result but it was a 50/50 chance based on the tolerance of the parts if it will latch high or low.
When building the binary counter the SR latch is actually a data flip-flop that has a wire going from the inverted output to the input.
This makes it so there will not be an invalid state. You can also build the data flip flops with JK flip flops but that is not required for the binary counter. For the ring counter, it will be required to use JK flip flops.
Pl, Demonstrate using Transistor the SISO 'D' FF shift register.(India)
I have a video on building a binary counter which is a shift register counter. In the 4-bit computer video there are two 7 stage ring counters which again are shift register counters. What application would you want to use the SISO for? I think building a serial-in parallel-out shift register would be interesting!
Applications: supply and receive the bits in serial MUL and DIV . Supply bits for old school sprites. We might want to skip this and rather have 15 colors plus transparency.
The advantage I see is that the speed is the same for all sizes, while with SRAM or counters to select a bit we have fan out. Of course for a lot of real world applications parallel operation (CMOS IC) beats this anyway. I guess that every serial connection like twisted pair or an antenna is serial to parallel as soon as possible. Also ADC output is only serialised in audio applications!