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I am not sure about the RC response @ 17:50. I don't think the voltage will be zero initially for sometime before rising for a linear ramp up signal because dVin/dt will remain same throughout. I think the start point will be origin itself but the RC constant will decide whether the output rises faster or slower than the input ramp. Please correct me if i am wrong
Sir first of all thank you to the content .Sir you explained in a good way .but I am requesting you plz make vedios on following type of cases 1) when a capacitor is connected at drain side of mos and pulse signal with some time period T applied what can be the output signal,how capacitor voltage varies 2) When cap is connected at source and pulse signal applied with time period T what can be the output signal,how capacitor voltage varies. 3) when caps are connected at drain gate and different signals like step ,pulse with time period T is applied how cap voltage changes All these cases for pmos and nmos . These kind of things are not present in books. In the interviews and in the written tests these kind of questions they are asking if you make a vedio on this it would be a great help for us After this when caps are connected to cmos inverters of different combinations I.e at Gate,source,drain ,gate and source ,source and drain ,gate and drain ,gate and source and drain and applying different inputs like step,ramp,pulse and observing how cap voltage varies and what will be the output signal in each case . As a subscriber I am requesting you make vedios on this topic . One vedio it will take 45 min time
Capacitors block the change in the voltage.So suppose I give the impulse from 0 to 5 so there is a sudden change in voltage.So it will block that change and at that time voltage should be zero not the maximum voltage or the caps will not charge.Caps don't charge in TS they charge in SS . If so then how can the voltage be maximum as per your explanation for a impulse in real life. I think you should come out of simulation world and be more practical. In real life there is no such thing as impulse .Even an impulse takes a time to rise and fall maybe of the order of ns or ps.That nano or pico becomes a steady state for the signal.In that staedy state the capacitor charge and discharge. Impulses are steps without the steady state theoretically but practically the steady states are so less we don't consider that and make those SS as zero.
Hi , Thank you for your comments. The purpose of these lectures is to create intuition and they help us in analyzing circuits. I agree , the impulse is not real and you may not see it in your lab. But In analog design ,we build on our theory and intuition to create any real working circuits.
Good explanation ramp response RC
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I am not sure about the RC response @ 17:50. I don't think the voltage will be zero initially for sometime before rising for a linear ramp up signal because dVin/dt will remain same throughout. I think the start point will be origin itself but the RC constant will decide whether the output rises faster or slower than the input ramp.
Please correct me if i am wrong
Hi. As for the initial current , it will start from 0 . I suggest you to plot it on LT-spice for clarity . Thanks
@@vlsiorg Ok I will check. Thank you for the reply.
I am still wondering, what will happen when you apply current as a step input to the capacitor?
capacitor will linearly charge
no R is linear the C (no inital value) will charge from 0 to linear line and then it close to steady state input Step Signal
tysm
Sir first of all thank you to the content .Sir you explained in a good way .but I am requesting you plz make vedios on following type of cases
1) when a capacitor is connected at drain side of mos and pulse signal with some time period T applied what can be the output signal,how capacitor voltage varies
2) When cap is connected at source and pulse signal applied with time period T what can be the output signal,how capacitor voltage varies.
3) when caps are connected at drain gate and different signals like step ,pulse with time period T is applied how cap voltage changes
All these cases for pmos and nmos . These kind of things are not present in books. In the interviews and in the written tests these kind of questions they are asking if you make a vedio on this it would be a great help for us
After this when caps are connected to cmos inverters of different combinations I.e at Gate,source,drain ,gate and source ,source and drain ,gate and drain ,gate and source and drain and applying different inputs like step,ramp,pulse and observing how cap voltage varies and what will be the output signal in each case .
As a subscriber I am requesting you make vedios on this topic . One vedio it will take 45 min time
Hi , I will surely try to make one such series .
Capacitors block the change in the voltage.So suppose I give the impulse from 0 to 5 so there is a sudden change in voltage.So it will block that change and at that time voltage should be zero not the maximum voltage or the caps will not charge.Caps don't charge in TS they charge in SS . If so then how can the voltage be maximum as per your explanation for a impulse in real life.
I think you should come out of simulation world and be more practical. In real life there is no such thing as impulse .Even an impulse takes a time to rise and fall maybe of the order of ns or ps.That nano or pico becomes a steady state for the signal.In that staedy state the capacitor charge and discharge.
Impulses are steps without the steady state theoretically but practically the steady states are so less we don't consider that and make those SS as zero.
Hi , Thank you for your comments.
The purpose of these lectures is to create intuition and they help us in analyzing circuits. I agree , the impulse is not real and you may not see it in your lab. But In analog design ,we build on our theory and intuition to create any real working circuits.