its the best course on youtube for learning computer architecture. teacher speed is little slow but we can change the playback speed. thanku nptel and all teachers.
4:33 - MAR and MDR connection diagram 6:40 - Summary of MAR and MDR connection 7:36 - PC and IR Registers 13:30 - Architecture of Example Processor 15:05 - Example Instructions 15:23 - Add R1, LOCA
if IR contains the content of memory location then what is the working of MDR because it also contain the content? what MDR actually do after instruction is to be taken by IR?
i think it is CPU who load the address to MAR of memory location that to be fetched and after data is read ,that to store in MDR then after cpu will execute the instruction.
it is not that memory knows that operand are in registers...we put/ write the code into the memory in particular instruction format that is fetched by the processor .....
I think I misunderstood somewhere at 10:50 . Correct me if I'm wrong but the sequence of steps must be: a) Instruction is brought into the processor and stored in the IR. b) Instructions are decoded in the IR when PC points to that particular instruction. c) The operands in the instruction are decoded to get the addresses and given to MAR. READ control signal is issued. d) The MAR fetches the data from Primary memory into the processor to MDR. e) Only then is the instruction interpreted and executed in the processor.
Why are these lectures so boring 😑😑😑😑 I have attended a guest lecture by professor Sengupta....and he awesome....here his colleague just making me sleep
its the best course on youtube for learning computer architecture.
teacher speed is little slow but we can change the playback speed.
thanku nptel and all teachers.
Very very fantastic explanation mam, I am a beginner to learn CA. Ur explanation is very very clear. Keep rocking mam...
This is indeed a really nice course .All aspects are covered appropriately.
see in 1.75x or 1.5x, otherwise u sleep
i am watching at 2.5x
🤣🤣
@@avisekhghosh2757 me too ;)
Elon Musk of future
i just started the course but i can feel its a great course.
Excellent course thanks teacher
4:33 - MAR and MDR connection diagram
6:40 - Summary of MAR and MDR connection
7:36 - PC and IR Registers
13:30 - Architecture of Example Processor
15:05 - Example Instructions
15:23 - Add R1, LOCA
Very clear and to the point lecture. Thank You.
Thank you very much for your convincing lecture.
Thank you for these lectures...
More than sufficient... Thanks 🙏
brother do u have ppts of these plz share that will be helpful
( 26:36 ) why we increment PC early before execution of previous location??
Please answer any one??
if IR contains the content of memory location then what is the working of MDR because it also contain the content? what MDR actually do after instruction is to be taken by IR?
IR only holds the instructions to decode it but MDR holds the data which is not directly stored in any kind of Register
14:03 what is the function of this ALU?
Is operands r registers ?
If both MAR and MDR are reading data and instructions from memory, then what is the basic difference between the two?
i think it is CPU who load the address to MAR of memory location that to be fetched and after data is read ,that to store in MDR then after cpu will execute the instruction.
MAR will specify the address from which the instruction/data to be read from the memory but that instruction/data is loaded into the MDR.
MAR takes up the address from which we need to get the data for MDR
How can I get the pdf
If the memory address is from 0 to 1023 then how memory address 2000 or 5000 is used?
now a days address size is of 32bit so it can store address of each bytes upto 4gb not only 1024 but 2^32 locations
In instruction,
ADD R1,R2
We fetch instruction from memory, but how memory knows that our operands are in these registers. Please answer mam/sir ASAP.
it is not that memory knows that operand are in registers...we put/ write the code into the memory in particular instruction format that is fetched by the processor .....
Basic operations, types of registers,working
I think I misunderstood somewhere at 10:50 . Correct me if I'm wrong but the sequence of steps must be:
a) Instruction is brought into the processor and stored in the IR.
b) Instructions are decoded in the IR when PC points to that particular instruction.
c) The operands in the instruction are decoded to get the addresses and given to MAR. READ control signal is issued.
d) The MAR fetches the data from Primary memory into the processor to MDR.
e) Only then is the instruction interpreted and executed in the processor.
already the information will be stored in the form of binary numbers in the memory then what is the need to decode that instruction?
its not technically decode its more like interpret and issue signals accordingly.
bish...stfu
But how would the computer know which binary pattern represent what operation
dont see her speed just lost in the way she explains ,we need more lectures maam , i m totally in love with way she delivers the lecture
Her speed is actually not an issue. Her lectures are pure gold🏅
@@ronaldbnjohnson834 same bro
too low audio
cant hear
These lectures are for those students who have some basic knowledge of COA. Else it will be difficult to understand .
This is on the point lecture with precision, university faculties don't have these much clarity .
What is BUS?
u use it for transportation.
more like ASS but without the AS and you have many porns shot on BUS...Fake Taxi Fake Bus
@@vibhas4686 mookhe libik?
@@spandansaha168 What th fuck is your problem asshole?? We are here to learn.
Memory: - Classification and types. Cache memory, direct mapped, associative mapped
and set associative mapped cache. cache replacement policies, write policy, unified, split
and multilevel cache, virtual memory, paging, segmentation.
Input Output System: 15
I/O buses, device controller, Interrupt and DMA. Interrupt driven I/O, Program
controlled I/O and DMA transfer.
Parallel Architectures: 25
Classification, SISD, SIMD, MISD, MIMD, Scalar, vector, superscalar and pipelined
processor, Pipelining, Instruction pipeline, pipeline bubbles, Hazards: -resource conflicts,
data dependency, branch difficulty. Vector computing, arithmetic pipeline, vector
and scalar register, chaining, scatter gather operations, vector-register processor,
memory- memory vector processor. Array processor.
Advanced concepts:
Branch prediction, super pipelining, Branch delay slot, Register file, superscalar
architecture, superscalar pipelines, superscalar branch prediction, out of order execution,
register renaming, Pipeline scheduling, dynamic scheduling and static scheduling
algorithms, reorder buffer and register renaming, Thronton technique and scoreboard.
Tomasulo algorithm and reservation stations. VLIW architecture: - EPIC architecture,
Multiprocessor systems: - Interconnection types. Cache coherence problem
SIR MAKE VIDEO ACCODING TO THIS SYLLUBUS
Aye Sabash😇
Why are these lectures so boring 😑😑😑😑 I have attended a guest lecture by professor Sengupta....and he awesome....here his colleague just making me sleep