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Thanks NPTEL, such concepts if I were to learn by myself, couldn't gather them all by myself.

I have watched this lecture, but unable to solve problem asking to calculate average memory access times.

Commenting for self reference. LRU replacement as an algorithm has similarities with insertion sort. Insertion sort: In each pass, if a value has to be moved to earlier position, all values between current and valid positions are moved one position up.

In Vertical microinstruction encoding, each encoded signal can represent only one control signal. Does this limit what we call a "micro instruction", which is control signal to activate one or more necessary circuit to perform single machine operation, to a "micro instruction" which can only produce single control signal to a single circuit per encoding.

To every one who are worried that ma'am didn't explain things just go ahead, you will understand instructions in next 2 lecture. So don't get demotivated and keep moving.

14:29 dont you still have to consider tA1 since to know you're missing you have to access level 1 first? i mean shouldn't it be tavg = H1tA1 + (1-H1)H2(tA1 + tA2) + (1-H1)(1-H2)(tA1 + tA2 + tA3)?

what aare the pre-requisite???

Thanks, madam You tought very clearly and thoroughly!

Good english used . Thank you .

00:14 Static and dynamic RAM are two types of semiconductor memory systems with differences in speed, density, volatility, and cost. 03:08 Comparison between SRAM and DRAM memory systems. 08:56 SRAM cell consists of two inverters forming a latch connected to transistors T1 and T2. 11:23 Static RAM cell operation and read operation 16:24 CMOS realization of NOT gate. 18:51 CMOS realization of not gate and six-transistor static RAM cell 23:31 Static RAM requires current flow only when accessed 25:53 One transistor DRAM cell requires periodic refresh due to charge leakage 30:26 Asynchronous DRAM vs Synchronous DRAM

Excellent course thanks teacher

14:03 what is the function of this ALU?

This course on Computer Architecture and Organisation has been designed very carefully, encompassing all the required concepts in proper sequence. I would like to thank Prof. Kamalika dutta and Prof. Indranil Sengupta for such an insightful course.

Now i will flex this knowledge in front of my professor 💀💀

How can I get the pdf

Just reading the slides, not explaining how are things done

21:42

End

Pillai student attendance here 😂

Very easy explanation. Thanks 👍

🙏🙏

tum chutiya ki tarah kyun pdhati ho

Keep uploading please 🥺

thank you mama or sir for this video , i requite keep upload

Are yaar , kuch samjha bhi do ya keval read kroge

ye madam ____ hai, ese kuch nhi aata. bus jo ppt maih likha hai use hi padh de rhi hai aur sirf ek-do baate apni taraf se phek rhi hai

padle exam hai tera kal

Good vdo after ❤

2 ghas jast khalela ubc 😂😂

Bro seems like Einstein 😮

Thank you sir & mam both of you for providing such a knowledge 😊

0:15

actually i have learnt more about cache then in my entire course of cache. thanks mam. one request. please put slides for download.

When I follow the bits through computer logic I feel as if I am looking at a single neuron in the human brain and measuring when it spikes. Now that we have AI, I see how CMOS gates in computers can simulate a brain almost. Fascinating.

I like you!

Superb

In single bus arch, MDR is not connected to the bus?

i dont know y you stopped uploading....but this is top notch study content...and this is THE BEST computer architecture playlist on the whole RUclips...

Please which book can I use to depth understanding these concepts

Extremely useful video. Thank You SIr.

Thank you ma'am

its very good lecture mam

These lectures are for those students who have some basic knowledge of COA. Else it will be difficult to understand .

4:33 - MAR and MDR connection diagram 6:40 - Summary of MAR and MDR connection 7:36 - PC and IR Registers 13:30 - Architecture of Example Processor 15:05 - Example Instructions 15:23 - Add R1, LOCA

One small correction - 36:47, In auto decrement before accessing the operand, the contents of this register are automatically decremented to point to the previous consecutive memory location i.e like --a NOT a--.

Please update title

Great explanation

a workstation uses a 1.5 ghz processor with a claimed 1000 mips rating to execute a given program mix. assume a one cycle delay for each memory access. i. what is the effective cpi of this computer? ii. suppose the processor is being upgraded with a 3.0 ghz clock. however, even with faster cache two clock cycles are needed per memory access. if 30% of the instructions require one memory access and another 5% require two memory accesses per instruction, what is the performance of the upgraded processor with a compatible instruction set and equal instruction counts in the given program mix? solution plz

Explained nicely.

Very clear and to the point lecture. Thank You.