Illustration of sampling delay in PWM convertersSamp delay final

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[@bobby9568]

Love the videos which include LTspice! ❤

[@sambenyaakov]

😊Thanks

[@tamaseduard5145]

👍🙏❤️

[@sambenyaakov]

Thanks

[@chaiyonglim]

Hi professor, I have seen papers/text book stated that having sampling delay will make the system to be non-minimum phase system (RHP zero), but if we model the delay to be exp{-sTd) like you did and look at the Bode plot as well as the step response like you did in 5:15, we don't see the non-minimum phase behaviour ( output step fall negative before rise ). If that is the case, theoritically we can add one LHP zero 10 times larger the cross over frequency to compensate the phase shift caused by the delay? Can you comment?

[@sambenyaakov]

Thanks for the contributing conversation. The definition of a non minimum phase system is that it does not obey the phase-magnitude relationships of basic poles and zeros. E.g. a single pole has a -20 db/dec drop and 90 degrees lag. The RHPZ is just one example. Since the sampling delay does not follow these templates The amplitude states constant while the phase drops) it is indeed a non minimum phase sytem.

[@RogovAB]

Thank you for this very informative lecture! Am I understand correctly that ADC triggering should occur much faster than characteristic time of the compensator response? Not sure, when this requirement can be failed. Usually we trigger ADC synchronously with PWM timer, and PWM register is updated only by the next period. This delay of about 1 period (or even shorter) would be always smaller then any characteristic time constant of compensator, wouldn't it? It seems to be a some alternative expression of Nyquist theorem.

[@sambenyaakov]

Not sure that I follow. A one period delay could be very significant. E.g. if the cross over frequency is say 1/5 of the switching frequency, the lag is about 70 degrees!

[@MishraKenhat-ju7jy]

Thanks for another great video Prof. I have a question. What do you mean by sampling delay? Is it the same as the sampling period?
If the calculation of the pid is within the sampling period we do not need to take care of this delay, right? I saw a video about this on @marcosalonsoelectronics and the expression for the effect of the sampling period is different

[@sambenyaakov]

There is sampling rate and sampling delay. The delay is betweem the time the error voltage is sensed and the time it changing the duty cycle. In digital control. the delay is about one switching period.