This is so awesome. High quality educational video for PCB designers. Been watching your videos everyday for a while now. I was wondering if you could go into how to fan out a BGA chip, how to determine the number of layers needed, as well via-in pad technology. Thanks!
Thanks, Zach, great video. It would be nice if you could add one more: a video that covers not only high-speed but high-voltage designs. Please cover information about important parameters and isolation capabilities of substrates when you have high voltage gradients (high voltage difference) both along the surfaces and across both sides. What must be taken into account when designing 1MOPP or 2MOPP (or MOOP) isolation through the board. It would be great if you could also define in Altium design rules or constraints for isolation between layers, not only creepage and clearance on the surfaces...
Thanks, we did one on high voltage materials, but not on high voltage design practices, so maybe I should add that to our (already very long) list of topics! You can watch the high voltage materials video here: ruclips.net/video/FqnUnwCHAzg/видео.html
Can please make a video on Properties to consider while preparing a pcb for use in space. Also, what about outgassing and flamibility in PCBs in space?
You have mentioned that tighter glass weave is better for high frequency. But these come in the thicker prepreg and may not be suitable to get the required impedance and track width. Also high resin content is preferred next to copper to avoid resin starvation. Any comments?
Well I guess I have a few comments: 1) you can use thicker prepreg for example in routing striplines and this will allow a larger width. If you just take a thin outer layer dielectric and put it into inner layers for striplines, the width might be too thin if you have a high layer count board, so you would need a thicker dielectric anyways. 2) You can use coplanar ground if needed to get to a thinner linewidth, which is very useful on surface layers. The coplanar ground adds to the self capacitance of the trace and will reduce the impedance, so you can use a smaller linewidth if needed. 3) You're right about resin starvation which will be a problem for growth of conductive anodic filamentation (CAF). It's something you will have to balance when looking at the overall build, if extremely long term reliability is important or you are operating with high voltages in potentially humid environment, then CAF may be important for your build.
Interesting to learn about the possibility of vias cracking under high temperatures with lower a lower Tg rating. How does this come into play when running through reflow? If a board is only rated for 130C, is there degradation when going through the assembly process?
Hi Andrew, not sure if you were being sarcastic down below. But my opinion is practically reflow can degrade a board. I have seen cheap manufactured boards from abroad that were operational in the product, but upon warranty repair were impossible to fix. So factor in the high-temp of reflow when considering life-expectancy of the product.
Hi, Mr Zach. I am Teddy from Ecuador. I have a couple years learning by myself how to make pcbs and specifically PCB design. I love these kind o videos and motivates me to keep learning about this fascinating world. I would like to become a professional pcb designer and I am currently finishing my degree in electronics and automation engineering. If it's possible it would be awesome to do an intership with you or in your company in order to grow profesionally. I hope this message could reach out your mailbox and I will be grateful to know some news!
for universal ac inputs that use 400v dc link, can we use fr4 materials? if not how do find the proper ones, one more question about the needed space between layers?
Space is chosen between layers based on the need for impedance control and power decoupling, or to ensure you hit a standard board thickness target. Some designs demand a thicker or thinner board, and this might require adjusting the layer thicknesses to hit those targets. For very high voltage/current boards, you may want to use thicker layers depending on the insulation requirements between conductors. For a 400 VDC board, yes you can use FR4 grade materials but you have to look at the Performance Level Category/Comparative Tracking Index for that material especially if you are designing to an industry standard like UL 746A, IEC 60112, or ASTM D3638. Materials that fall in these categories are rated for different voltage ranges based on their leakage current. The other important point that is not specified in those categorizations is the curing agent that is used in the material. Materials that are built with different curing agents can exhibit CAF growth that eventually leads to failure. Phenolic cured PCB laminates are preferrable at high voltages.
Yes, typical reflow oven temperature can exceed 200 Celsius. With high Tg board materials, the temperature will only slightly exceed the Tg value for a lower amount of time and with lower total expansion compared to a low Tg board material.
@@Zachariah-Peterson OK, so that means that, with a low Tg board, once the components are on, you shouldn't be surprised if copper pads lift when you try to rework or tweak the board?
@@petersage5157 Actually you should be surprised, I have never seen that happen to one of my boards, although I'm sure it has happened to someone. Manufacturers test the peel strength to ensure that he copper adhesion meets IPC standards, so even if there is a large thermal excursion you wouldn't expect the copper to start lifting off the board, and certainly not during reflow. I don't know what is the specific force they test for, but in order to prove compliance they will test for that. What's really problematic is in HDI or in high aspect ratio through-holes. In HDI, microvias or stacked blind-buried vias are known to fail during reflow if the aspect ratio is too high. This is what motivated the IPC to issue a reliability warning about microvias in 2019. For high aspect ratio through-holes, the barrel plating could fail if it is deposited with a DC process, this is because the plating will not easily deposit along the via wall due to copper depletion in the plating solution inside that via barrel. I've been told by one of the large US fabrication houses that they use pulsed plating specifically to address that problem in high aspect ratio through-holes, it creates a more even plating along the via barrel.
@@Zachariah-Peterson Thank you so much for sharing your knowledge! To be honest, my most recent experience reworking a board was modding a Valve Junior many years ago; several pads lifted while I was desoldering the original components from the single-sided board. Since then anything that wouldn't fit in a 1590B stomp box had been turret boards and terminal strips, which are much more forgiving when it comes to ham-fisted desoldering. Sounds like the standards may have improved a bit over the past decade.
Videos like these are so valuable for those trying to become better engineers. Thank you, Zach!
This is so awesome. High quality educational video for PCB designers. Been watching your videos everyday for a while now.
I was wondering if you could go into how to fan out a BGA chip, how to determine the number of layers needed, as well via-in pad technology.
Thanks!
Thank you Mateo! I'll add it to our long list of requested topics!
Thanks, Zach, great video. It would be nice if you could add one more: a video that covers not only high-speed but high-voltage designs. Please cover information about important parameters and isolation capabilities of substrates when you have high voltage gradients (high voltage difference) both along the surfaces and across both sides. What must be taken into account when designing 1MOPP or 2MOPP (or MOOP) isolation through the board. It would be great if you could also define in Altium design rules or constraints for isolation between layers, not only creepage and clearance on the surfaces...
Thanks, we did one on high voltage materials, but not on high voltage design practices, so maybe I should add that to our (already very long) list of topics!
You can watch the high voltage materials video here: ruclips.net/video/FqnUnwCHAzg/видео.html
Another great pcb video.
Glad you enjoyed it
Very nicely explained, Thanks Zach.
Additional important information to the material would be flammability. For example RO4003 can't be used in military or automotive applications.
Excellent information...!!! i like this video series. Thank you so much!!
Thanks Diego, Glad you liked it!
Can please make a video on Properties to consider while preparing a pcb for use in space.
Also, what about outgassing and flamibility in PCBs in space?
We filmed your video request this week!
@@Zachariah-Peterson thankx a lot
@@Zachariah-Peterson can u provide the name or link of that video...i am not getting it on the page
@@goodtogo2626 It's in editing right now, should be on the channel in a couple weeks
@@Zachariah-Peterson Ok.
You have mentioned that tighter glass weave is better for high frequency. But these come in the thicker prepreg and may not be suitable to get the required impedance and track width. Also high resin content is preferred next to copper to avoid resin starvation. Any comments?
Well I guess I have a few comments: 1) you can use thicker prepreg for example in routing striplines and this will allow a larger width. If you just take a thin outer layer dielectric and put it into inner layers for striplines, the width might be too thin if you have a high layer count board, so you would need a thicker dielectric anyways. 2) You can use coplanar ground if needed to get to a thinner linewidth, which is very useful on surface layers. The coplanar ground adds to the self capacitance of the trace and will reduce the impedance, so you can use a smaller linewidth if needed. 3) You're right about resin starvation which will be a problem for growth of conductive anodic filamentation (CAF). It's something you will have to balance when looking at the overall build, if extremely long term reliability is important or you are operating with high voltages in potentially humid environment, then CAF may be important for your build.
Info on CAF and how it relates to the laminate spec would be appreciated.
Interesting to learn about the possibility of vias cracking under high temperatures with lower a lower Tg rating. How does this come into play when running through reflow? If a board is only rated for 130C, is there degradation when going through the assembly process?
@@Zachariah-Peterson Thanks, Zach! Appreciate you taking the time to provide a detailed answer to my question.
Hi Andrew, not sure if you were being sarcastic down below. But my opinion is practically reflow can degrade a board. I have seen cheap manufactured boards from abroad that were operational in the product, but upon warranty repair were impossible to fix. So factor in the high-temp of reflow when considering life-expectancy of the product.
Hi, Mr Zach. I am Teddy from Ecuador. I have a couple years learning by myself how to make pcbs and specifically PCB design. I love these kind o videos and motivates me to keep learning about this fascinating world. I would like to become a professional pcb designer and I am currently finishing my degree in electronics and automation engineering. If it's possible it would be awesome to do an intership with you or in your company in order to grow profesionally. I hope this message could reach out your mailbox and I will be grateful to know some news!
for universal ac inputs that use 400v dc link, can we use fr4 materials? if not how do find the proper ones,
one more question about the needed space between layers?
Space is chosen between layers based on the need for impedance control and power decoupling, or to ensure you hit a standard board thickness target. Some designs demand a thicker or thinner board, and this might require adjusting the layer thicknesses to hit those targets. For very high voltage/current boards, you may want to use thicker layers depending on the insulation requirements between conductors. For a 400 VDC board, yes you can use FR4 grade materials but you have to look at the Performance Level Category/Comparative Tracking Index for that material especially if you are designing to an industry standard like UL 746A, IEC 60112, or ASTM D3638. Materials that fall in these categories are rated for different voltage ranges based on their leakage current. The other important point that is not specified in those categorizations is the curing agent that is used in the material. Materials that are built with different curing agents can exhibit CAF growth that eventually leads to failure. Phenolic cured PCB laminates are preferrable at high voltages.
I'm confused about the glass transition temperature. Isn't this quite a bit below the typical dwell temperature of a reflow oven?
Yes, typical reflow oven temperature can exceed 200 Celsius. With high Tg board materials, the temperature will only slightly exceed the Tg value for a lower amount of time and with lower total expansion compared to a low Tg board material.
@@Zachariah-Peterson OK, so that means that, with a low Tg board, once the components are on, you shouldn't be surprised if copper pads lift when you try to rework or tweak the board?
@@petersage5157 Actually you should be surprised, I have never seen that happen to one of my boards, although I'm sure it has happened to someone. Manufacturers test the peel strength to ensure that he copper adhesion meets IPC standards, so even if there is a large thermal excursion you wouldn't expect the copper to start lifting off the board, and certainly not during reflow. I don't know what is the specific force they test for, but in order to prove compliance they will test for that.
What's really problematic is in HDI or in high aspect ratio through-holes. In HDI, microvias or stacked blind-buried vias are known to fail during reflow if the aspect ratio is too high. This is what motivated the IPC to issue a reliability warning about microvias in 2019. For high aspect ratio through-holes, the barrel plating could fail if it is deposited with a DC process, this is because the plating will not easily deposit along the via wall due to copper depletion in the plating solution inside that via barrel. I've been told by one of the large US fabrication houses that they use pulsed plating specifically to address that problem in high aspect ratio through-holes, it creates a more even plating along the via barrel.
@@Zachariah-Peterson Thank you so much for sharing your knowledge! To be honest, my most recent experience reworking a board was modding a Valve Junior many years ago; several pads lifted while I was desoldering the original components from the single-sided board. Since then anything that wouldn't fit in a 1590B stomp box had been turret boards and terminal strips, which are much more forgiving when it comes to ham-fisted desoldering. Sounds like the standards may have improved a bit over the past decade.
Any discussion for Td?
Hi Rutwij, are you referring to the decomposition temperature?
Do you offer consolation services
Yes, contact me on LinkedIn, you can find a link to my profile in the video description.