I read a paper a couple of years ago about an ISA designed to autovectorize typical loops. I can't find the paper, but a key trick there was conditional behavior for each element in the vector. Notably, loads and stores were conditional, so that an "if" statement in the loop could be vectorized regardless of memory operations inside the "if". I don't see anything like that in this proposal...
*Tom Hanks introduces RISC-V vector extension*
I read a paper a couple of years ago about an ISA designed to autovectorize typical loops. I can't find the paper, but a key trick there was conditional behavior for each element in the vector. Notably, loads and stores were conditional, so that an "if" statement in the loop could be vectorized regardless of memory operations inside the "if". I don't see anything like that in this proposal...
"oh my good so many colors in the slide - I am not making a vector unit" -- his talk is kind of funny ;)
Roger Espasa de la FIB? :)