SV-3: The Power of Inheritance | Synopsys

If randomization is the right hand of verification using SystemVerilog, inheritance is the left hand. This webisode will enlighten you on what inheritance means in OOP, and how it easily enables you to create different tests for verification without affecting other users of the verification environment on your team and without having to change your existing tests and test environments.

[@brucelu4782]

Thanks for the class. 5:46 is quite confusing, gen object in top module is an instance of Generator, but gen.pkt is assigned to pkt_da_3, how is the virtual function involved here? BTW, in the extended Packet class, should the "BadPacket" class name be "Packet_da_3"?

[@AkbarRajaei]

00:00
02:25 inheritance extended class (subclass)
02:50 base class (super class)
03:05 new properties and new methods
03:22 replace object
04:02
04:28 overriding (change existing methods)
04:51 super keyword (reuse base method)
05:26 virtual (make method virtual), 05:51
06:00 virtual in extended class

[@VEERUIITK]

Good one