Q. 6.6: Design a four‐bit shift register with parallel load using D flip‐flops. There are two contro
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- Опубликовано: 7 сен 2024
- Q. 6.6: Design a four‐bit shift register with parallel load using D flip‐flops. There are two control inputs: shift and load. When shift = 1, the content of the register is shifted by one position. New data are transferred into the register when load = 1 and shift = 0. If both control inputs are equal to 0, the content of the register does not change.
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I think the shift is the one having a higher priority as when shift is 1 the register shifts without relying on the value of the load
agree
Your load is the opposite of shift in truth table
use multiplexer dude.. also new data is transferred only when s = 0, l = 1.. why did you put don't care in shifts?!
sir when both load and shift both are 1 then what will be gate
This video seems wrong. It is a parallel load circuit. Your load is serial.
he only draws one stage, there are four stage.
You have to Connect third And Gate input is 1 1 Shift And Load why because given condition is connectd to 0 0 ...
Sir how can we do it with jk flipflop
Hello cse b, nitt