Q. 6.10: Design a serial 2’s complementer with a shift register and a flip‐flop. The binary number
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Q. 6.10: Design a serial 2’s complementer with a shift register and a flip‐flop. The binary number is shifted out from one side and it’s 2’s complement shifted into the other side of the shift register.
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Problem solutions of the book Digital Design by Morris Mano and Michael Ciletti: • Q. 6.1: Include a 2‐in...
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These are some life-saving tutorials! Thank you Professor!
How do you get the first diagram?
I see you just write down the diagram first and explain it.
But I don't know how can I get the diagram first.
Thank you.
Where do we give the input for this circuit?
can't we just do negation and then half adder with 1 to the i/o
In two's complement arithmetic, to negate a binary number, WE should:
Keep all the bits unchanged up to and including the least significant '1'.
Invert all the bits after the least significant '1'.
In the circuit you've provided, if the input to the 'D' flip-flop (DFF) is '1', then its output (Q) will also be '1'. If this output is directly connected to an XOR gate with the bit value 'x' being processed, the XOR output will be the inverse of 'x', which is incorrect for the first '1' encountered when scanning from the least significant bit towards the most significant bit. After the first '1' is copied, subsequent bits must be inverted.As an example if we have 1010 the correct complemet is 0110 but this circuit we give us 0100.How ca we correct it and thank you .
Where can I get verilog code for this question?
I have watched this video 4 times over and have learned nothing
You genius sir❤
great job!
Thank you! Cheers!
at 3:19, you said 0 xor 0 is 0, which I don't think is correct.
Correct only
Where will the input be fed into?Since the input is connected to the out put how can we feed the input?Thanks
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@@koushikvarma3899 Did you guys do the code lol
The title should be 6.10, not 6.20
Thanks a lot. I have modified the title and description.
Kehna kya chahte ho?
Hello CSE b, nitt
hey!