EFCL Summer School - Keynote #4: Memory-Centric Computing

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  • Опубликовано: 5 июн 2024
  • EFCL Summer School on Open Source IC Design and Computer Architectures (efcl.ethz.ch/efcl-summer-scho...)
    Track 4 Lectures (safari.ethz.ch/memory_systems...)
    Keynote Talk #4: Memory-Centric Computing
    Keynote Speaker: Prof. Onur Mutlu
    Date: June 6, 2024
    Slides (pptx): people.inf.ethz.ch/omutlu/pub...
    Slides (pdf): people.inf.ethz.ch/omutlu/pub...
    Recommended Reading:
    ====================
    Intelligent Architectures for Intelligent Computing Systems
    people.inf.ethz.ch/omutlu/pub...
    A Modern Primer on Processing in Memory
    people.inf.ethz.ch/omutlu/pub...
    RowHammer: A Retrospective
    people.inf.ethz.ch/omutlu/pub...
    RECOMMENDED LECTURE VIDEOS & PLAYLISTS:
    ========================================
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    Digital Design and Computer Architecture Spring 2022 Livestream Lectures Playlist:
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    Digital Design and Computer Architecture Spring 2021 Livestream Lectures Playlist:
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    Featured Lectures:
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    Interview with Professor Onur Mutlu:
    • Interview with Onur Mu...
    The Story of RowHammer Lecture:
    • The Story of Rowhammer...
    Accelerating Genome Analysis Lecture:
    • Accelerating Genome An...
    Memory-Centric Computing Systems Tutorial at IEDM 2021:
    • IEDM 2020 Tutorial: Me...
    Intelligent Architectures for Intelligent Machines Lecture:
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    Computer Architecture Fall 2020 Lectures Playlist:
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    Digital Design and Computer Architecture Spring 2020 Lectures Playlist:
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    Public Lectures by Onur Mutlu, Playlist:
    • Onur Mutlu - Future Co...
    Computer Architecture at Carnegie Mellon Spring 2015 Lectures Playlist:
    • Lecture 1. Introductio...
    Rethinking Memory System Design Lecture @stanfordonline :
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Комментарии • 2

  • @matthewvenn
    @matthewvenn 20 дней назад +1

    Surprising, shocking, inspirational - loved the keynote, happy I saw it live!

  • @Tapajara
    @Tapajara 17 дней назад

    A RISC processor requires more memory accesses to accomplish the same things as a well-designed CISC processor. So our infatuation with RISC is partly to blame for the waste you talk about. Having a more concentrated instruction set is the equivalent of keeping your most frequently used subroutines close to the CPU. That is what CISC is all about.