I would love to see an experiment where you place the same V reg circuit multiple times on a board but using different heat sinking techniques. I’ve always been wary of vias in pads so have put a heat sink next to or surrounding a component, then attached it to the thermal pad with multiple traces. Also wondering about whether tented/untented vias has an effect and exposed copper pours vs ones covered in soldermask.
A temperature and humidity IC I used recommended a smaller thermal pad on the PCB than on the back of the IC, presumably so you can keep the thermal vias away from the solder and prevent wicking.
I've been wondering about thermal vias in my designs and when they're necessary. I often wonder whether some of the designs I see are cargo culting it; this video has shown me that my designs haven't needed them - so far, anyway - and that the examples I've seen that have made me wonder, have probably been overkill. Thank you so much! 🙏
Another tip for vias on exposed pads; You can divide exposed pad into multiple areas and then separate them with solde mask and place vias into this soldermasked areas therefore you can eliminate the solder wicking completely. But as Phill said in his video you should small via holes like 0.2-0.3 mm so tents doesn't rip off. Also you can consider filling or plugging your via that would solve the wicking without a doubt but again it adds some cost.
How to add a Thermal pad? Is it just in Layout to select Place -> Pad -> then I chose template "s670c50_2670034071" to obtain a rectangular copper Pad. However I am unable to change the dimensions of the copper Pad. If anyone knows how to implement it. It would be of great help!
Great video, thanks! Also, guys, keep in mind solder paste stencil - you can control solder winking. But when designing custom stencil do not forget about it's mechanical strength. Also you can calculate required volume of paste to keep vias filled and component soldered. About unbalance with copper - it can be solved with increasing preheating time (if you communicate directly with technologists). But copper unbalance always bad, even when your board fully unbalanced - it can be twisted while heating. Some components are bad by design. My my least favorite - balun BALF-SPI2-01D3 by STM, because of it's very light for BGA and have very disbalancing position of ground pin. Best regards, Phil!
Is it okay to route signals over power plane gaps, if the plane on the other side of the signal layer is a solid gnd plane? Lets say the distance between power plane and signal layer is 0.1mm and the distance between signal and gnd plane is 0.1mm as well.
really you are a good instructor on youtube about pcb design and rules , actually i start as an embedded engineer throughout my self learning . i learn lot of arduino based hardware and software last few months ago i started projects based on stm32 series , your all videos help me lot thanks. waiting for newones
Plugged vias will be more expensive and tenting shouldn't be done under an IC pad. I haven't had a problem yet with using smaller via drills as suggested in the videos, and being thoughtful with placement within the thermal pad.
Phil; do you know the opinion of Brooks to thermal via’s? -> what is your opinion? “Designers sometimes drop vias between a plane or pad to conduct heat away to another plane or heat sink. This is thought to be an effective way to cool a component that generates a lot of heat at a concentrated point on a board.” “The small plane does not help much in cooling the pad. Each thermal via helps cool the pad another increment. But the larger plane (by itself) substantially cools the pad above it” “In each of the cases, the addition of thermal vias offers some additional cooling, but in the case of the larger plane and the heat sink their marginal contribution is much smaller.” From PCB design guide to via and trace currents and temperatures - Brooks
Very nice and brief introduction into thermal management! This is a must if ever you're designing for space electronics(i.e.: Sat systems). The vacuum of space is not friendly to boards. Else, the mech./thermal engineers will throw tomatoes at you.
At around 7 minutes, you're suggesting using unused regions of layers as duplicate power pours, alternating with ground layers. This is to reduce heating, as well as to lower induction. But obviously, alternating power and ground layers make a capacitor. Does this become significant? Or is that how you're combating induction? Love that !u talk about aspects that don't get discussed much
Great video as always. You didn't go over filled/capped vias which would allow you to put as many thermal vias under the part as you want without having to worry about solder wicking. Of course that will add cost, but it looks to be standard with JLCPCB for boards with 6 or more layers.
Phil, as you know I've been following along while making an audio mix/eq/hub for my office. Lately I found the STM32H7 can process samples in real time. No need for buffering. Just use the SAI FIFO's which add lots of helpful functionality and interrupts. The downside is... a stereo 16bit@48K input and 5 or 6 of your "PeakFilter" and it's using 69% CPU already. I really needed it to do 2 EQ channels and support 4 inputs and 2 or 3 outputs. Core is running at 480Mhz. Unless I can make those Peak Filters go twice as fast I'm out of luck. Same for 96kHz. Do you think there is "that" much performance in moving to ARM optimized BiQuad library filters? Given it has a DPFPU.
By the way, I don't think buffering gains anything is real terms (processing 1000 samples will still take 69% of the time it takes to send them). Clock cycles per sample is the important ratio and it's around 69% CPU. In fact if I push it a little further, it drops the Tx to 24K and skips interrupts. The SAI interface duplicates the last sample from the FIFO so the output is down sampled to 24k. I have tried with 2 samples (1 stereo pair), 4 samples and the FIFO max 8 samples. It still spends 69% of it's time in the interrupt and 90% of that time is running the 6 peak filters :(
The tip on thermal relief of through hole grounds is serious, I've had some 6 layer boards that required I preheat the entire board to solder. Now I reduce the spoke width and make any hand soldered component pad oversized (oval) to allow better contact with the iron tip. Another all linear regulator thermal workaround is to cascade them to distribute the heat over multiple linear regulators, or use a current pass transistor to assist the regulator with of some of the current. The later became very useful during the pandemic when IC availability was extremely volatile, I've never had the need to go full linear supply so the combination of switching and linear was always viable. Except during a pandemic when the switchers are all out of stock and backordered for years.
Very true! And yes - that's right, cascading linear regulators or using a switcher followed by a linear regulator is another way of doing this (if cost, space, design, etc.. allows).
Just to add to what you said, don't forget the humble resistor can be used to take some load off linear regs for practically free. Depending on the application of course.
Perfect timing, I'm in the middle of designing a BLDC driver and I was wishing for a good video on thermal design
Awesome, glad to hear that, Michael - hope all goes well with the BLDC driver design :)
I am also designing a BLDC Driver based on the RP2040 and DRV8316
I would love to see an experiment where you place the same V reg circuit multiple times on a board but using different heat sinking techniques. I’ve always been wary of vias in pads so have put a heat sink next to or surrounding a component, then attached it to the thermal pad with multiple traces.
Also wondering about whether tented/untented vias has an effect and exposed copper pours vs ones covered in soldermask.
A temperature and humidity IC I used recommended a smaller thermal pad on the PCB than on the back of the IC, presumably so you can keep the thermal vias away from the solder and prevent wicking.
Niceee content. When is the advanced PCB design course will be released, phil?
I've been wondering about thermal vias in my designs and when they're necessary. I often wonder whether some of the designs I see are cargo culting it; this video has shown me that my designs haven't needed them - so far, anyway - and that the examples I've seen that have made me wonder, have probably been overkill. Thank you so much! 🙏
Glad to hear that - thank you for watching!
Another tip for vias on exposed pads;
You can divide exposed pad into multiple areas and then separate them with solde mask and place vias into this soldermasked areas therefore you can eliminate the solder wicking completely. But as Phill said in his video you should small via holes like 0.2-0.3 mm so tents doesn't rip off. Also you can consider filling or plugging your via that would solve the wicking without a doubt but again it adds some cost.
How to add a Thermal pad? Is it just in Layout to select Place -> Pad -> then I chose template "s670c50_2670034071" to obtain a rectangular copper Pad. However I am unable to change the dimensions of the copper Pad. If anyone knows how to implement it. It would be of great help!
Great video, thanks!
Also, guys, keep in mind solder paste stencil - you can control solder winking. But when designing custom stencil do not forget about it's mechanical strength. Also you can calculate required volume of paste to keep vias filled and component soldered.
About unbalance with copper - it can be solved with increasing preheating time (if you communicate directly with technologists). But copper unbalance always bad, even when your board fully unbalanced - it can be twisted while heating. Some components are bad by design. My my least favorite - balun BALF-SPI2-01D3 by STM, because of it's very light for BGA and have very disbalancing position of ground pin.
Best regards, Phil!
@15:45 how about plugging the vias? This will increase the cost but how about the thermal benefits?
Is it okay to route signals over power plane gaps, if the plane on the other side of the signal layer is a solid gnd plane? Lets say the distance between power plane and signal layer is 0.1mm and the distance between signal and gnd plane is 0.1mm as well.
really you are a good instructor on youtube about pcb design and rules , actually i start as an embedded engineer throughout my self learning . i learn lot of arduino based hardware and software last few months ago i started projects based on stm32 series , your all videos help me lot thanks. waiting for newones
Always top quality content.
Thank you, Peter!
Hi,
any free software for thermal simulation for pcb
What do you think about plugged/tented vias? Would that be better with the regards to solder wicking?
Plugged vias will be more expensive and tenting shouldn't be done under an IC pad. I haven't had a problem yet with using smaller via drills as suggested in the videos, and being thoughtful with placement within the thermal pad.
Phil; do you know the opinion of Brooks to thermal via’s? -> what is your opinion?
“Designers sometimes drop vias between a plane or pad to conduct heat away to another plane or heat sink. This is thought to be an effective way to cool a component that generates a lot of heat at a concentrated point on a board.”
“The small plane does not help much in cooling the pad. Each thermal via helps cool the pad another increment. But the larger plane (by itself) substantially cools the pad above it”
“In each of the cases, the addition of thermal vias offers some additional cooling, but in the case of the larger plane and the heat sink their marginal contribution is much smaller.”
From PCB design guide to via and trace currents and temperatures - Brooks
Can you PLEASE show how to do double sided pcb design in altium??
Thank you
Does he shift his voice pitch down?
Very nice and brief introduction into thermal management! This is a must if ever you're designing for space electronics(i.e.: Sat systems). The vacuum of space is not friendly to boards. Else, the mech./thermal engineers will throw tomatoes at you.
Keep it up! 100k subs soon :)
Thannk you very much🙏
At around 7 minutes, you're suggesting using unused regions of layers as duplicate power pours, alternating with ground layers. This is to reduce heating, as well as to lower induction. But obviously, alternating power and ground layers make a capacitor. Does this become significant? Or is that how you're combating induction? Love that !u talk about aspects that don't get discussed much
Great video as always. You didn't go over filled/capped vias which would allow you to put as many thermal vias under the part as you want without having to worry about solder wicking. Of course that will add cost, but it looks to be standard with JLCPCB for boards with 6 or more layers.
Do you review our project ?
Phil, as you know I've been following along while making an audio mix/eq/hub for my office.
Lately I found the STM32H7 can process samples in real time. No need for buffering. Just use the SAI FIFO's which add lots of helpful functionality and interrupts.
The downside is... a stereo 16bit@48K input and 5 or 6 of your "PeakFilter" and it's using 69% CPU already.
I really needed it to do 2 EQ channels and support 4 inputs and 2 or 3 outputs.
Core is running at 480Mhz. Unless I can make those Peak Filters go twice as fast I'm out of luck. Same for 96kHz.
Do you think there is "that" much performance in moving to ARM optimized BiQuad library filters? Given it has a DPFPU.
By the way, I don't think buffering gains anything is real terms (processing 1000 samples will still take 69% of the time it takes to send them). Clock cycles per sample is the important ratio and it's around 69% CPU. In fact if I push it a little further, it drops the Tx to 24K and skips interrupts. The SAI interface duplicates the last sample from the FIFO so the output is down sampled to 24k.
I have tried with 2 samples (1 stereo pair), 4 samples and the FIFO max 8 samples. It still spends 69% of it's time in the interrupt and 90% of that time is running the 6 peak filters :(
Do you think of making a video about electromagnetic effect in pcb design?
Inductance is a concept I always struggle a bit with. Would love to hear more about it.
Great video!
hey Phil it would be really cool if you could make a video discussing CPLDs
Hey Max, I'll try to cover that in a feature video. However, for now I have a few different ideas lined up!
Yet another gold nugget. Keep em coming
Thanks, Biko!
Is there any recommendations for thermal considerations for high power SMT LEDs?
If possible, use an aluminum substrate.
Thermal vias which run through to a metal heatsink on the opposite side of the board is another way to do it.
Thumbnail worked👍
This channel is one of the best PCB design channels on RUclips, thank you for sharing your knowledge Phil.
Thank you very much for your kind comment!
It's an interesting video, clear explanation, thank you.
Thanks, Amine!
❤🔥
You're videos lit as always. Thanks for share this information
Thank you for watching!
Nice video
Thanks!
superb, thanks Phil
Thanks, Dean!
❤ 👍
👍🙏❤
First!!!
Second
The tip on thermal relief of through hole grounds is serious, I've had some 6 layer boards that required I preheat the entire board to solder. Now I reduce the spoke width and make any hand soldered component pad oversized (oval) to allow better contact with the iron tip. Another all linear regulator thermal workaround is to cascade them to distribute the heat over multiple linear regulators, or use a current pass transistor to assist the regulator with of some of the current. The later became very useful during the pandemic when IC availability was extremely volatile, I've never had the need to go full linear supply so the combination of switching and linear was always viable. Except during a pandemic when the switchers are all out of stock and backordered for years.
Very true!
And yes - that's right, cascading linear regulators or using a switcher followed by a linear regulator is another way of doing this (if cost, space, design, etc.. allows).
Just to add to what you said, don't forget the humble resistor can be used to take some load off linear regs for practically free. Depending on the application of course.