SiFive: Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads

Presented by Chris Lattner, President, Engineering and Product, SiFive.
Tremendous progress has been made in the last year towards bringing RISC-V vector (RVV) extensions to market in both hardware implementations and supporting compiler technologies. SiFive has gone a step further with the inclusion of new vector operations specifically tuned for the acceleration of common neural networking tasks. We will demonstrate how these new instructions, integrated with a multicore, Linux-capable, dual-issue microarchitecture, with up to 256b wide vectors, and bundled with TensorFlow Lite support, are well-suited for high-performance, low-power inference applications.
The Linley Spring Processor Conference featured technical presentations on chips and IP for AI applications, embedded, data center, automotive, IoT, and communications. The conference also covered new CPU architectures, networking, memory, security, SoC design, AI training, and other processor-related topics.
For more info on the Linley Spring Processor Conference 2021 you can visit our proceedings page:
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