I would recommend an improvement to this code: set the shift register BACK to zero after the conversion is done in the last 'if' block shift_register [19:8] = 0; This will avoid the shift register continually continuing up to a larger and larger number every time the 8-bit number changes. This, I think, will save data/time as the number of times the changes will continually increase Great video. The verbosity in your code made it easier to follow. Very clear!
Thank for your clear explanation, I learned a lot. Will the code design by finite state machine better? Because your code mixing sequential circuits and combination circuits in one block. Looking forward to your reply🥹
In the first if statement: "if (i==0 & (OLD_eight_bit_value != eight_bit_value)) begin" why do you assign the temp_* values to the upper bits of the shift_register? This is confusing. Why not assign to all 0's which is what they should be at the beginning of the binary to BCD conversion? Thank you for the tutorial!
I had the same question. Turns out that this algorithm its called Double Dabble. Every time you shift, the number its doubled. When you have something equal or greater than 5 in a nibble, after the shift the value in that nibble will be greater than 9. When this happen you want to carry a bit to the next nibble. So before the shift you add 3 because after the shift it will became a 6, which means the next nibble will receive the carry and the current nibble will retain the residue. Hope this will be helpfull for someone :3
if 2's compliment 8 bit binary number is there than what changes should I do in the above code? I want to make 2's compliment 8 bit binary to BCD converter in verilog. In 2's Complement 8 bit number, MSB [bit 7] is sign bit.
I'm having the same problem, I recreate the example of the table, but with a integer of 3500, I think the shift register should be 28 bit long, eventhough don't know how big i counter should get, if someone know please let me know
@@chaiinito9092 in theory it should work the same, 16bit is complemented by 2 so it should work. 12bit isn't so stick to the powers of 2 in terms of bits.
I would recommend an improvement to this code: set the shift register BACK to zero after the conversion is done in the last 'if' block
shift_register [19:8] = 0;
This will avoid the shift register continually continuing up to a larger and larger number every time the 8-bit number changes. This, I think, will save data/time as the number of times the changes will continually increase
Great video. The verbosity in your code made it easier to follow. Very clear!
Thank you!
Thank for your clear explanation, I learned a lot.
Will the code design by finite state machine better? Because your code mixing sequential circuits and combination circuits in one block.
Looking forward to your reply🥹
If you could post videos about PISP, PIPO, and SIPO that would appreciated.
In the first if statement: "if (i==0 & (OLD_eight_bit_value != eight_bit_value)) begin" why do you assign the temp_* values to the upper bits of the shift_register? This is confusing. Why not assign to all 0's which is what they should be at the beginning of the binary to BCD conversion? Thank you for the tutorial!
Plz make a vedio about digital alarm clock.
Hi Mukul, I'll keep it in mind, no promises right now. Thanks for the request!
I used this algorithm successfully in verilog but when I tried adapting it to vhdl I haven't been successful, anyone know why?
do we need a testbench to run our code ?
Felix Alexander i can use a vector waveform to test it actually if the fpga is not available
Felix Alexander yes you can input some values but there is no need to create a testbench to run the waveform
Hope you enjoyed this tutorial! Let me know what was something you learned through this video!
Your videos are simply great knowledge pack.
Just a suggestion, use cursor highlight 👍👌
Thank you so much, I'll use it for future videos (I've already done the next one, but after that, for sure). Thank you again, means a lot!
hello!
could you tell me why addition by 3 is necessary for when one's, ten's or hundred's place is greater than or equal to 5?
I had the same question.
Turns out that this algorithm its called Double Dabble. Every time you shift, the number its doubled. When you have something equal or greater than 5 in a nibble, after the shift the value in that nibble will be greater than 9. When this happen you want to carry a bit to the next nibble. So before the shift you add 3 because after the shift it will became a 6, which means the next nibble will receive the carry and the current nibble will retain the residue.
Hope this will be helpfull for someone :3
if 2's compliment 8 bit binary number is there than what changes should I do in the above code? I want to make 2's compliment 8 bit binary to BCD converter in verilog. In 2's Complement 8 bit number, MSB [bit 7] is sign bit.
Did you made it? I'm searching for the same thing
What is the shift register value to be given for 12 bit integer?
I'm having the same problem, I recreate the example of the table, but with a integer of 3500, I think the shift register should be 28 bit long, eventhough don't know how big i counter should get, if someone know please let me know
@@chaiinito9092 in theory it should work the same, 16bit is complemented by 2 so it should work. 12bit isn't so stick to the powers of 2 in terms of bits.
it's REPresents. not REEPresents. lol 1:04 1:13
I used this algorithm successfully in verilog but when I tried adapting it to vhdl I haven't been successful, anyone know why?