RAM timings explained 0
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- Опубликовано: 22 июл 2024
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#RAM #overclocking 
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I cannot express how much I love the "I give up edition" videos. In spite of Buildzoid's reluctance to do them, which I kind of understand, I think they are the best content on this channel. Bookmark material.
Even if it's on a topic I've no interest or real need to know, anytime I see crazy hair in the thumbnail or "I give up edition" in buildzoid's videos I ALWAYS WATCH! Cuz there's always something either super insightful or super conical in the video every time, plus the comments about "overclocked hair" are too funny lol
Buildzoid officially hates this comment.
We officially love this content. And Buildzoid.
so far in 9 mins i know more than 10 years of trying to learn the basics, granted i have not dedicated serious time to learning but well done i do not take in information very easily.
You spent too much time trying to understand the basics! You should have just jumped over to the more advanced stuff so you would have known more in a shorter span of time!😁
6x6x6x lvl on 8c lvl 10k 12clvl x2 24c 24x 12x2 300mhzx2 to8c 400x2 = 24.800mhz
RAM OCer calls RAM names for 30 minutes
"Tightening timings doesn't make your RAM work harder. It tells your RAM 'I am willing to wait less time for you to complete this action.'"
Understanding that is a fundamental of RAM overclocking, and we need to hear it! Now, if only we had a video explaining what each timing did so we had an idea as to what's a reasonable amount of time to shave off. 😉 (This is a joke, please don't kill me.)
It’s true for all overclocking really.
I'm more in the camp of "If we had a video that explain what each timing did *with commentary on how that particular thing affects various performance scenarios* we would have an idea as to which timings it's really worth having a go at, and which will lead to diminishing returns outside of competitive overclocking"... But I assume that sort of normie reasoning isn't going to get me any favours :P
Shorter wait times translate into more tasks, so more work over a period of time
@@firage that's how i've decided to look at it, any timing I can shave down should result in more work being at least possible in a certain amount of time (provided what I shaved down is used :P) but then I really only tune my ram to nudge my minimum framerate up (still cheaper then a 5800X3D :P)
just like turning up the thermostat doesn't make the furnace run any faster/hotter . It just affects how often the furnace operates.. similar , not the same.
i laughed my ass off to "i give up edition"
"No matter how bad this take is, it's what you're getting."
This is why we love Buildzoid. xDDD
@@benjaminoechsli1941 at least he tried to reshoot
Self-refreshing is super useful.
It allows a bank of memory that is not currently accessed to just be clocked to do it's own refresh. No involvement from the controller beyond initiating the refresh and letting it tick along is necessary.
Was it also that row is also refreshed when you access it. I think one my friend did patter generator that used SDRAM and used specific address sequence that it full filled refresh requirement so he just read data "constantly" and never did refresh when it was sending pattern.
@@LimbaZero If the SDRAM is small enough and your read rate is high enough that you can cycle through it you would indeed avoid refresh.
Is the self refresh enabled via status/control registers and do you know if that is part of the initial calibration process? I'm trying to find out if the Micron DDR memory is automatically configured and uses the "self refresh" signals to automatically keep DDR contents from decaying because the normal memory controller (MIG 7) does not allow the user to turn "User Refresh" on. When User Refresh is on, the user is supposed to send refresh commands using "app_ref_req" and if the user doesn't, then the contents should decay. I have a board with a custom memory controller based on the MIG 7 that has refresh disabled. I write to DDR, wait a few seconds, then read that memory address. However I do not observe the DDR contents decaying, even when resetting the board to an unprogrammed state and repeating. If I fully cut power to the device and wait, then upon power up I observe DDR decay. It should be noted that in simulation turning the user refresh to "ON" behaves exactly as it should, its only in hardware that I am not getting the behavior I expect.
Thanks for not giving up on us!
Basically:
Read too early, data is corrupted
Refresh too fast, data is gone
Refresh too slow, believe my or not, data is gone.
I get the joke, but it's not refreshing too fast. Rather, it's not waiting for a refresh to finish. Hmm, analogy.
Serve customers before fish is plated, data is corrupted.
Undercook fish, data is gone.
Wait too long to cook fish. Believe it or not, data is gone.
It's not perfect, but I'm too tired to come up with anything better.
@@arthurmoore9488 It's a sacrifice I had to make to be slightly funny. I was also thinking of adding more, but I was going to be more convoluted.
We appreciate your time spent brute forcing and finding out the sweet spots for the rest of us :) your dedication is appreciated. I'm about to go back and watch some old X299 content because my comp is getting long in the tooth and I haven't updated it's OC in 3 years or so and it's been BSODing. I'm so glad to have easily understandable and quickly accessible material for it so I can reduce my OC and fine tune it again. Thank you!!! Oh and I was inspired by gamers Nexus and you to get into overclocking and the last time I tried I got the world record for my hardware :) the endorphins felt so good. Thank you thank you thank you
The thumbnail looks like something out of the NecronoMicron.
His desktop background is a pentagram with RAM terms scattered throughout, so the observation is fitting. ;P
Man, I knew memories were dumb but I wasn’t aware they were *that* dumb. Basically works by speculation of timing and good luck getting it on time. Damn!
Not quite speculation. The memory chip manufacturer says it will take at least X nano-seconds to do a thing, but that is a worst case for all of the chips they sell at that spec. When safe timings are set in the memory controller they always allow at least that amount of time - so no speculation is required. That's the whole point of having default timings set by the module's SPD data. But when you overclock, you are saying "I wonder if my memory chips can actually do that thing in Y nano-seconds, where Y is smaller than X. That is where the speculation comes in. If you're lucky, after a bunch of testing, you may find that your memory always works with the Y nano-seconds setting, regardless of address and data patterns and regardless of the temperature (within reason). If it does, then great, you are speculating no more - you have now overclocked your RAM by some small amount.
I believe people would like to know:
1. What is the order of OC (RAM or CPU 1st)
2. What you should prioritize overall - lower CL or higher MHz
3. What other timings should you prioritize
4. What timings should be changed if I change timing X (like some timings are linked together or there is some correlation between some timings)
Accurate
@@RUclipsTookMyNickname.WhyNot but they're unlikely to get +3 fps in games though.
On the other hand, in my experience adjusting timings does help with stability and pacing of frame times, thus overall improving the feeling of it..
1. RAM 1st if you intend to do RAM. Though most probably go backwards as arguably CPU is easier to set.
2. Higher MHz allow you to keep around same ns latency in CL/RCD/etc. while lowering ns latency in timings like RRD WTR and others (I.e. those that as bz states in video can't go below certain value in register), thus improving your bandwidth while overall keeping best-case latency around the same (and lowering worst-case latency)
3. Other than CL: RRD + FAW, WTR, RCD (if you can), tertiaries, RTP/WR seem to be most impactful on actual performance, especially compared to defaults. REFI likely easiest to set, RFC below stock values too, as it gets blown up if you follow jedec specs. On DDR5 CL doesn't matter as much, secondary/tertiary are the more important settings, go watch the 3 vids exploring tuning timings live on this channel and then some other vids with proper settings in them.
4. This is a tougher one, go read a proper guide instead of this youtube comment from a noob /s
There are quite some correlation / non-existent registers even that should be mentioned/explained, but this really is more in-depth, seriously, go look at the other documentation.
1. RAM first unless you're going to do BCLK overclocking i think. (Assuming cooling for the memory won't be an issue once you finish OCing your CPU)
2/3. Higher MHz, then low primaries, then low secondary timings, then the rest. CL matters less than tRCD.
3. The primaries, especially tRCD (which is the main reason Samsung B-die is the best memory around) GDM off and usually getting command rate 1 stable, but not always. having enough ranks to do rank interleaving. Low tRFC and tFAW for secondary timings as well as the tRRDs.
4. AFAIK all of them are correlated, i just try out values people using the same memory ICs i have got stable and adjust.
Either way beyond a certain point you're getting diminishing returns for gaming. I don't even bother with tertiaries if i got secondary timings i'm happy with stable. For dailying you're better off with a config that's going to lose you a bit of .1% performance but you know won't ruin your data.
1) finding a high stable RAM speed should be done first and then CPU… tuning down the memory if required, you will find a middle ground at some point
2) you find the lowest of what ever this is called here is the equation for what ever it is
1 divided by memory clock in GHz take that number then multiply by CL for the number
Example 1 / 6.4 = ans X 32 = 5 [the lower this number the better]
3) not a clue
4) not a clue
this is better information then the "what does each ram timings do?" question ...lol...you offer insight to this that I've never found anyplace else .... to cool!!!!! thanks.....
A veritable timing salad. Good video, thanks!
It's magic, end of video.
>2:26
Self refresh lets laptops turn off the CPU memory controller during sleep/standby so the battery doesn't drain when it's in your bag. Dunno if desktops use it.
I'd guess sleep moded uses it then.
@@ActuallyHardcoreOverclocking Yes, when suspending to RAM, you need to transition into the self-refresh mode because everything else that could perform refreshes is turned off during suspend.
What an inspiring Pentagram.
And now my t-shirt finally makes sense!
Finally the content i have been looking for without locked behind paywall
When it has "I give up edition" I know I'm gonna like it lol
Thank you for this! It definitely helps to understand the basics.....but yes I understand that it's still trial and error.....awesome video!
I’m not an overclocker. I’m here to see BZ do epic shit and explain the EE stuff I don’t understand to me. Here you did both things, thanks 🙏
I'm of a similar sort. Don't overclock, I just like learning about all the little details that make a computer work. I would've never guessed this is how timings work.
Thanks buildzoid, nobody explained any of this to me in all my 25 years
Thanks for that. Now onto the next video in series. This one was extremely informative.
i wanted to sleep, checked RUclips for sleeping material (Gamers Nexus benchmark Video), a wild buildzoid give up Edition with 34 minutes of rambling about ram timings appears and now i have sleep deprivation but know that DDR Memory is really dumb backed up by 30 minutes of Information.
thanks buildzoid :D das good stuff.
waching your videos the last 5 years or so paid off. already knew most of it
I wouldn't be surprised if this video blows up someday and reaches millions of views. It's tough to find content on the nuances of memory timings.
This is quality content right there!
Saved this for future reference when I build a PC later and go into customizing parameters.
Thanks, I probably never learned that much within 30 minutes
I think this might be one of the best videos you have ever made.
Thanks a lot for this explanation... very clear, interresting
So I just draw that pentagram and do a blood sacrifice to Samsung or Micron.
I just found this channel and am finding this content both hilarious and extremely informative. Thank you
I have learned so much from this video and it's made me realize so many of my misconceptions on how memory works. I thought that you could damage the ram by trying to push it too far, the way you theoretically could with overclocking a processor.
Thank you for this. 👍
It works exactly the same as with a CPU.
The higher the temperature or voltage the lower life span the microchip will have.
Also microchips will degrade overtime with high voltage or temperature and then require more voltage to run at the same settings than before.
The capabilities of a CPU memory controller is also a big part of memory overclocking and the memory controller can degrade overtime as well if you feed it too much voltage.
You can't damage microchips by directly increasing the speed they run at however. It comes as a side effect of higher power and cooling requirements.
@@markokuosmanen I'm talking about memory timings not overvolting
@@esotericbear9829 I'm just saying you can damage the RAM stick by overclocking depending on the factors I mentioned.
From your message someone could get the idea that you can't or if you only meant the speed (clock speed/timings) then you could get the idea that you can damage a CPU by only increasing the clock speed it runs at which isn't true.
@@markokuosmanen The primary focus of this video was memory timings. My comment was in reference to the memory timings. I now realize there is zero damage that could be done by changing the memory timings. You are way over thinking this. It was a simple compliment for the video.
@@esotericbear9829 You can actually do damage by changing the timings if the memory becomes unstable as a result and then causes corruption of the operating system and therefore damages the software installation. You just can't damage the RAM stick (the hardware) itself. Also if you update motherboard BIOS with unstable settings you could possibly brick it.
It is important to specify things in order to prevent misunderstandings.
This was great, thanks.
This is an EXCELLENT explanation of the general memory operation. Great job!
I know how memory works and have a good understanding why the timings are needed How long timings take and how to find the perfect balance is magic for me
trial and error.
@@ActuallyHardcoreOverclocking As a student of electronic engineering it is magic
we only think of logic and how long the logic takes, but capacitors in logic are just magic that they hold data to me
(And yes i know how it works but this is so hard to get working that we can just do it every day so reliable is the magic)
@@vollkornbrothd1342 True, it's insane that everything works!
I like how BZ tells how "dumb" memory chips are. It's actually interesting to see that stuff like this still exist in 2022. Its kinda like early programming where you didn't have standard communication protocols for sending and receiving data and waiting for acknowledgement. You just sent a bunch of data and tried timing it so you didn't fill the buffer and prayed the data go to its receiver in the right order :) It kinda have its merits, cause If you can get those timings set just at the magic value for what the hardware can manage I'm sure you have much less latency than if you just set an arbitrary "acknowledge" command that have high enough delay for everything to be ready. Simplicity is often the best but more tricky to code.
@@vollkornbrothd1342 a lot of "magic" for future electronic engineer, imagining your report on something complex to your customer or chief... Well, it's really magic!
thanks for all the vids and i consider it as educating myself for an in depth understanding.....more vids and more power
As someone who currently only practices memory overclocking in theory, I found this video very insightful.
Thanks for the awesome video! This is the best and simplest explanation I came across, why we have memory timings and why some memory ICs perform better than others.
This is amazing! Thank you so much for this video!
I appreciate your vids and the knowledge you bring every time.
This video has been a really good explainer for me: I hadn't appreciated that you're simply changing how long you're willing to wait on operation completion.
Thanks!
Thanks BZ for getting us to understand so much more than we did before watching this fantastic, out of this world video!🥰
G'day Buildzoid,
It's gotta be so frustating constantly getting lazy people asking "I have (Insert Brand & Spec), What OC Settings do I use?" especially when as you have REPEATEDLY shown us in videos it doesn't work like that because...
Firstly Motherboard Memory Topology + Layer Count can Drastically Limit the RAM OC Abillity of the same DIMMs on Different Boards,
Secondly like your i5 & i9 have shown the CPUs Memory Controller can Drastically Limit the RAM OC Abillity with the same DIMMs,
Lastly even the Same Spec DIMMS like same Spec CPUs & GPUs due to Manufacture Quality can have widely different OC ability,
I'd just like to say how much I appreciate your work because thanks to finding your channel through your PCB Breakdowns for GN I have learned lots about how to buy Quality products & then with a little effort on my part using your guidance get the best out of them.
Awesome Video! Thanks for dumbing that down for us!
Bro you need your own Murch that says "The Thing Is" I'd definitely buy a shirt
As one that started playing around with tweaking RAM timings based on your videos, but with no real idea of how it relates, this was quite educational. Thank you.
Please continue the educational content like this it's so good.
24:00 "When you lower a memory timing, you aren't telling the memory chip 'Hey you have to go faster' - you're saying 'I am willing to wait less time for this operation to complete'" - This was so good at clarifying what goes on with memory timings, in one go 👍thanks! Now it's easy to understand (and explain to others) exactly why the timings need testing and may or may not work even if they're set by the motherboard or XMP or w/e.
Great Video man
When I was taking EE and calculus in college I would often meet problems I couldn't solve. If I couldn't solve it, I would grab a beer. I would then reexamine the problem 30 minutes later. If you can't solve. Repeat. Trust me, it has lead to more than a few creative "solutions". Lol
YES FINALLY this is golden educational content I might download this series of videos so they are 100% safe bc they are hands down the best on ram timings
I cant believe it was too expensive to implement an interrupt line ...
Great piece of information, anyways!
Absolutely classic
The problem with memory timings, as you've rightly pointed out, is that there are several methods of achieving each. You'd actually have to have a logic diagram of how, say, a write cycle is achieved in a given memory chip - as well as the specs for the DRAM cells themselves - in order to predict how many clock cycles at a given frequency it will take to do a particular function, and even then, this will vary with age, temperature, voltage, silicon quality, and the way the chip's internal gates are constructed. Since manufacturers don't provide this information, you CANNOT predict ANY optimal timing for a DRAM module any more than you can predict how much of an overclock you'll get on a random CPU sample!
Like you said, you've gotta just keep trying shorter and shorter timings until a given timing doesn't work. There is no shortcut. This is why your public experiments on different DRAM chips and their minimum timings are so valuable to the rest of us.
You can do the measurement and parameter extraction to attain model parameters the same way the manufacturers do. Reverse engineering models from samples is pretty routine business. Once you have that anything can be predicted by simulation.
@@Ormaaj You can calculate values via simulation based on sample specs, but the next run of chips will vary based on manufacturing (the "silicon lottery") and will change with age due to gate oxide breakdown and electromigration, as well as dialectic breakdown within the (capacitive) cells themselves.
As a freakin normie who basically never really intent to properly overclock anything but is curious about IT, this is very informative.
So thank you so much!
Even though those memory is "dumb", it is at the same time amazine how engineering can see, make, read and understand how those thing works in ns. It take skill to do that. I'm sitting here and like, now, now and now.. wow that fast.. well FASTER due to nano second. How the hell they come up with that? Tecnology is a wonderful thing.
Brilliantly done. 👏👏
I would have no motivation to do anything with ram if I didn't know what it did. The fun part of overclocking is the brute force trial and error part of it.
lmao this thumbnail is like a conspiracy diagram I love it. Your videos are great buildzoid - as a CompE I think more people need to appreciate how much the low level affects their experience
This is amazing!
Cool I've been looking for this type of video
Really helpful video. Thank you.
best. video. ever.
New favorite video!
i love the “did you not go to school”
Really cool, it was a bit hard watching the whole 34 mins but this was A LESSON, thank you a lot
Super helpful video, thank you!
Your doing God work! This will help a lot of people. I will say though, people need to understand that changing memory timings / overclocking can corrupt windows while your testing different things. I highly suggest using a spare OS drive for memory overclocking until you know its stable. Also know where the clear CMOS button/jumper is :)
Thank you! 👍
Self refresh is feature that allows the DRAM to refresh itself without the clock, therefore saving power. You can think of it as a standby mode which is faster to come back from versus deep power down with data being kept.
LOL Buildzoid crushing the hopes and aspirations of new and aspiring overclocker
thanks for the advice!
Knowing what timings do ahead of time means you know which timings are more important for your workload.
This video is so good.
thx for the lesson
I swear that diagram looked like some kind of pentagram to revive a Techno-Demon...
If you think this can revive a tech-demon just wait until you see his wallpaper...
good effort!
turns out I had no idea what the timings are actually for ;o]]
thx Buildzoid
Thanks!
It's ok memory chip, don't believe what the bad man says about you /soothe
Class. 💪 👌where’s my fff ing data?!?!
anyways...so...great video my man
@Actually Hardcore Overclocking: You said you weren't aware of what the "Self-Refresh" does: The memory chips have an internal row counter, and issuing the self-refresh command allows the memory chip to refresh a row, then increment the counter (which will roll-over to zero when the final row is refreshed) and the memory controller does not need to have its own row counter for the refresh tracking, but is able to do other memory operations while the bank of memory that has been issued the self refresh command does its refresh operation. One of the timings the controller tracks tells it how long it must wait before issuing any commands to that bank of memory. [Note that I'm talking about "banks" at the higher level of the motherboard DDR sockets, not the internal banks within each DRAM chip.]
Also, the self refresh command comes in two flavors: The currently select bank within the chip can be refreshed, or the refresh all command can refresh all banks on the current row.
The self refresh operation does go all the way back to SDRAM (ca. 1998?).
Edit:
1) I have described from memory the essentials of what self refresh has been since SDRAM (ie: PC-66) came out. I think self refresh was present in Fast Page Mode and/or EDO DRAM, but I'm not 100% certain of that.
2) All memory chips that I have seen (SRAM, DRAM, Fast Page, EDO, SDRAM, DDR, DDRx,...) are truly dumb devices, and any hardware utilizing memory simply needs to know how long to wait at any stage of access to the memory.
3) Thanks for this video. You called it the "I give up" edition, but you did a very good job of giving a nice overview of how memory timings work and it seems that you were actually fairly concise in your description and as accurate as one can be in giving an overview.
This is great stuff! What might be a good follow up is the relationship between timings, e.g., tRRDS and tFAW. Also, the relative impacts of some of the more useful settings, or even the highest impact settings for performance. I can think of two silly categories: shitty RAM throughput approach, shitty RAM latency reduction approach. That kind of thing.
1:50 and Micron's explanation already looks as a recipe to invoke Beelzebub... promising.
Believe it or not, it would be pretty easy to simplify things. It would just be much slower. Speed versus complexity is fun.
Remember, if they can shave $0.10 from a chip, times 10 Million chips, they've saved the company a million dollars. So, it's perfectly reasonable for a company to pay a whole team for a year to come up with some horribly complex solution that will save that little bit of money from every chip.
Thank you for taking the time to explain all of this, yeas it doesn't really help to OC (it does a little) it made me understand the basics and how things work, now I understand why you need to stress test the memory after the OC to check if the timing you set are inline with what the memory is capable of. Sorry it took me so long to finally watch this but didn't have time.
good video.
the reason i wanted to know this stuff other than just basic curiosity is that I've been testing the impact of each timing on fps in OW and I'm trying to construct a model for why one timing matters a lot and others not at all
also need to know how each timing is dependent on others to identify if my results are hampered by bottlenecks elsewhere
Nice! :D I am late to the party, but videos like this are really important.
I love tinkering with OC on my pc, and I am willing to invest the time, but there simple is no understandable guide out there for what to do.
"Just trail and error" is what most guides tell you, but thats not actually true, obviously...
From this video i learned:
1. Timings have a minimum.
2. Some timings can have weird behavior depending on volts and temps.
3. And most critically: memory follows a step by step order of operations. Your goal is to reduce idle time, and the only way to find how long these operations take, is by testing the memory.
But what I keep wondering about is if these timings are at all calculatable...
Say.. timings A B and C. Is A followed by B, followed by C.
If the timings are independent, I can focus on A, then B, then C.
Or is (by approximation?) C = A +2B and the timings are interdependant...
If that is the case, if I change timing B, I can also adjust timing C - which could save me A LOT of intermediate testing?
I guess knowing what memory timings do will help us more to ignore those ram timings that help the least to performance, it sucks to spend a lot of time tuning tRCDPVPMVPPVEGPCUDPTXTEXE or whatever's random timing not knowing if it will increase performance
cheers!
omg that explains so much
I wonder if an fpga could be set up to use it's own internal memory structures for controls and then test an external stick of DDR memory to analyse it's timings at different temperatures.
I can imagine people paying for a stick that has been analyzed with known good timings on it. Can even edit the data on the spd :)
A lot of the timings are dependent on temperature and would have to be confirmed at quite high chip temp to be safe/stable and it would be easy for such a system to test effects of voltage changes.
I imagine the ram manufacturers and distributors have such and FPGA and that's how they bin the chips.
I wonder if it's possible to write software that can test and set the best timings for any memory stick.
❤️
Gold!
On the refresh, the refresh command activates then deactivates (pre-charges) a set of rows in all banks, and it takes 8192 normal refresh commands (over the typical 64ms refresh window) to refresh all of the memory.
The 2^18 (262144) cycle refresh would result in a refresh window of a bit over 1 second, which is likely to result in the contents of infrequently accessed portions of memory degrading over time unless the memory is kept cool enough.
I finally understand how memory works, well... at least those parts of the memory that was in this video, which is still better than having absolutely no idea of anything other than low timings usually means faster RAM, it's also nice to know that it doesn't matter what each timing do because at the end of the day the RAM won't communicate with you that which of those timings are set to too low.
Thanks a lot for the video. One question on DDR5, you mentioned it is just so much better than DDR4. Can you make a video to explain the difference? Like the depth of your video in terms of technical details. Cheers!
As much as I'm looking for more knowledge of memory OCing, I'm not watching these vids for that. I'm just genuinely curious as to how memory operates.
From my understanding now, basically when OCing you're finding the limit that your memory can pretty much already complete the task (I.e. if your timing is 18 clocks but it finishes in 12 clocks, you're waiting another 6 clocks)?
I love this content, its super informative!
yes if your memory is capable of doing 12 but it's set to 18 you're losing 6 cycles for no reason so by OCing you find out what your memory is actually capable of but you shouldn't expect miracles because most are already binned and set close to the limit from the manufacturer, except Bdie.