Using High-Bandwidth Memory (HBM)

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  • Опубликовано: 20 авг 2024
  • eSilicon’s Tim Horel talks with Semiconductor Engineering about HBM and how that integrates with ASICs at advanced nodes.

Комментарии • 3

  • @trumanhw
    @trumanhw 4 года назад +1

    Wait ... 60 ... MB/s ...? I'm going to assume (if DDR4 x 4 channels is the limit under discussion) 100 GB/s ... which, acquiescing to data nomenclature would be in bits -- and therefore, 800Gb/s ... with perhaps an 80% real-world performance vs. theoretical ... no..? I'm guessing he just mixed up with unit ...? Or is there a reference to something else I missed...limiting things between it..?

  • @trumanhw
    @trumanhw 4 года назад +1

    One more little comment ... I'd imagine that Mr. Horel (Doctor..?) probably has a pretty bad ass pedigree ... I think he kind of deserves an introduction... I'm guessing he has a PhD, is maybe a EE or something ... maybe even created pioneering work in fundamental physics; who knows. But he deserves to have some of the highlights of his accolades credited to him ... as I could see some little nitwit coming here and picking on him for saying mega instead of giga or something. :)

  • @trumanhw
    @trumanhw 4 года назад

    Could I suggest as a topic perhaps elaborating on what an interposer is ...?
    Don't be SATA
    *As captain obvious, it's my duty to point out what you all know: That it's every specialist's charge to keep their technology from being what SATA + spinning rust was **_for decades_** !! ... That is, let no element of the architecture's **_ecosystem_** be the year-in and year-out bottleneck throttling all other elements of the architecture's performance. Making all other progress invisible bc we're at the mercy of one crappy component.*