Intel Performance Leadership in 2025: Beyond Nanometers
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- Опубликовано: 30 май 2024
- Everyone talks about 14nm, or 7nm, but what does it actually mean? Nothing.
But using numbers is an issue, because people will always list numerically. Intel has had enough, given that TSMC and Samsung 7nm skipped a hard node, so while Intel was all ++++, the other two were slowly decreasing numbers. To that end, Intel is aligning itself with the industry better with a new node renaming.
Oh, there was also some roadmaps too. A path to performance leadership in 2025.
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0:00 It's happening!
0:13 Sponsor: Linode
0:30 Intel Accelerated with Roadmaps!
1:08 Intel 14+, 14++, 14+++
2:53 Intel vs TSMC vs Samsung
4:11 10nm SuperFin
4:23 Intel 7
4:47 Intel 4
5:20 Intel 3
5:44 Intel 20A
6:20 RibbonFETs on 20A
7:12 PowerVias on 20A
8:28 Intel 18A on 2nd Gen EUV
9:35 Performance Leadership
9:59 EMIB
10:30 Foveros 2nd Gen
10:51 Foveros 3rd Gen Omni
11:56 Foveros 4th Gen Direct
12:30 Node Roadmap Slide
13:55 U R A SHIL
15:18 Cat Tax
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![[10] Mike Davies, Director of Intel's Neuromorphic Lab](http://i.ytimg.com/vi/p3fEXkmwXXA/mqdefault.jpg)
"Intel says 20A is coming out in 2024", I will buy you a 20A processor of your choice if they are on sale in 2024!
(I would probably even extend that to 2025 as Intel has been so poor at delivering on roadmaps over the last few years!)
Yeah process node production vs product on shelves; this announcement was very much the former
@@TechTechPotato Hey Ian, is Intel 20A a rebranded (licensed) IBM 2nm/5nm? The timing, transistor structure images and recently announced 'collaboration' just seem to line up. IBM also said that 2nm will be ready for production by around 2024
If 20A is in mass production by 2028 i'll be impressed
Their 2024 CPUs will be 20A. That is 20A at 12V or 240W idle.
Not that I believe they will actually deliver - I will call you out on your offer in 2024, hopefully intel is able to pull the trick this time. Its always bad to have the market reduced to less competitors.
It's a shame they're not going for density, though understandable given that as a measurement of performance neither node size or density really are a perfect judge...
Would have been nice to have a standardized size to compare everything by
For that, TSMC and Samsung would have to agree. Intel alone going for density will confuse others and especially IFS customers who are used to these nm names from other foundaries. Intel is just leveling the playing field here in my opinion
@@AkashPatel1995 yes right
yeah but at least density is a measure of the tech used to produced it
even density is a bit tricky one. what do you measure to measure density? are you just measuring how much SRAM you could cram on a mm2 wafer? or is it logic gates? or what? there's no standard on what to measure either, so it's not "standardized" by any means.
The issue there is everyone measures density different (as in, not all transistors are the same and not all devices are equivalent, e.g. NAND2 vs flipflop). Also, different libraries on the same node have different densities. It would get more inconsistent quicker, and more chances to play games, e.g. high performance libraries used in leading edge are typically anywhere from 50-80% the peak quoted density of the high density libraries for low power operation.
20 Angstrom? They should have called it 10^25 Planck. Much more room to shrink numbers in the future.
50 years from now, Intel rolls out its new 100P architecture. At least, we think they do, because it's so darn small you need an electron microscope to have a chance at looking at it.
@@benjaminoechsli1941 A neutrino microscope. :-)
The size of a silicon atom is ~2 angstrom. I hope I'll live long enough to hear Intel marketing explain to us how their 2A transistors work.
@@lolowfi lol they won't explain because it's established that it's fake
I'm not really happy with "nanometer" in the name of a any node if it's just a marketing term. It's as wrong as substituting MT/s with MHz.
On the other hand, Intel 7 feels like something is missing. They should use an N suffix (7N) and proceed with the A suffix later down the road.
Yeah, I was thinking along those lines too. It really needs a fake unit, almost
What about "I" for Intel, the Intel 7I process, or even better, the Intel I7 process, followed by Intel I4 and Intel I2! Intel, I'll send you my address to mail the check.
@@TechTechPotato tbf, isn’t the version of nanometer used in node naming right now fake? Lol
@@Testbug000 Nanometers are real, it is the value before the unit that is fake. If you change the unit or postfix after the value, the value can still be some arbitrary number without being "wrong" because it honestly doesn't mean anything (instead of as of now, dishonestly not meaning anything).
@@Testbug000 no that is Intel propaganda
How do you go from "Full use of EUV" and then the next step forward is "increased use of EUV"???
Full use is usually 'in every segment', meaning front end of line (FEOL), middle (MEOL), and back (BEOL). Might only be one layer in each segment
@@TechTechPotato I think you missed his point completely, Intel said Full Use of EUV, and then followed that with increased use of EUV. If your already at full use, 100%, how are your going to INCREASE past 100% use?
@@michaelkeudel8770 I think you did not understand Ian answer. A CPU is made of multiple segment, and each segment is made of multiple layers. With full EUV intel intended that they used EUV for at least one layer in each segment. So all the segments use EUV, bit not every layer is EUV. It is a bit misleading because there are still non-EUV layers, that’s why they can increase the use of EUV in the next generation.
@@51m0n397 I'm designing and building Intels EUV vacuum control system, have been for almost 3 years now, I know what EUV is.
Intel makes anything possible ;)
"Intel are going to skip the number 5 for some reason."
RIP the number 6.
It has some bad magical meaning. Like lots of elevators don't have 13th floor.
Actually the scale goes down by 70% so it goes like 14,10,7,5...
@@Ya39oub_G Samsung has 8 and 6 though
@@MaxIronsThird
It's to double the number of transistors on the same area.
Here is a video about it :
ruclips.net/video/ROS008Av4E4/видео.html
Or instead all these companies could simply put the density of transistors per unit area...
That's not a single metric tho. It depends on the kind of transistor, and each node has a set of libraries that offer varying degrees of PPA.
But that doesnt sound science fiction enough! Using such small nanometers I think just captivates a lot of people due to how hard it is for our brains to visually comprehend the extremely tiny size of nanometers. But they already jumped the shark. They cant advertise a true gate width of say 14-40nm when they been selling people on brand new 5nm. Its funny how they market it. for things we can visualize and understand, bigger number = better. Like a larger screen. But for such tiny sizes the smaller it is the more we struggle to visualize it so marketers have taken advantage of it to make it the small nanometer= super advanced over ur head science stuff.
@@WhenDoesTheVideoActuallyStart i understand, but 'nodes' is a single meaningless metric though. Transistor density means something physical though.
Even density isn't the only thing that matters, or there wouldn't be low power, high power (etc) variants of nodes and the types of finfets used wouldn't be such big news. Makes it extremely difficult to agree on any single metric because silicon of equal density can perform very differently.
@@Steamrick Yeah, in the end there's no way to simplify process nodes into a single number that can reflect their characteristics. Samsung is very competitive on density, but the efficiency of their nodes tends to lag behind TSMC (And then you get things like Ampere).
This is such amazing stuff. I started in the industry in 1967. What an incredible evolution.
Awesome content, following your channel nearly a year. Highly recommend
Awesome video as usual! I always anxiously await your analysis when big industry news drops.
Read the article this morning. Wanted to talk to you about this and of course you fully beat me to it with a video. Ty!
I can LITERALLY see it!
Thanks, Steve.
Back to you @gn Steve
Can Intel execute? Well how many EUV machines will Intel get? That is the first step, but is not enough to guarantee success and execution so yeah, 🤞
That's the important question. This isn't the first time Intel promises awesome products for the future, but they weren't able to deliver on their promises. What guarantee do we have they'll be able to deliver now?
I was surprised about the comment that INTC will be one of the first customers for the High NA machines from ASML. Although I haven't read their recent earnings report and/or if they mentioned Intel.
@@1idd0kun there's a new CEO. Let's wait how he handles alder and raptor lake
@@angeleduardorojasgonzalez858 Alder Lake and Raptor Lake were pretty much done before Gelsinger even signed on the dotted line. I think everyone knows there's nothing he can do about the hardware that's launching before 2024.
@@stefangeorgeclaudiu you should be familiarized with what Bob Swan did in 11th gen with the sudden change to 14++++nm. He would've delayed the launch but here we are. Everything before 2024 was already done yes that's true but if there is something else to upgrade I'm sure he won't hesitate to state it.
Thanks for covering the packaging stuff too
Pet the kitty, God damn it. Also, thank you, highly informative, always appreciate your insight.
I say intel hit the character limit and couldn't add any more + so they had to rename it
I'm shame of myself being an engineering student. I literraly don't understand most of the things you talk about. Still I watch you talk to motivate myself.
This is probably the second best solution for Intel. The best would be to get the general consumer to understand that these numbers don't mean anything between different companies.
And as a consumer you're not buying a manufacturing node, you're buying a chip. The chip has properties that are influenced by the node but not decided by it.
It's good that Intel is moving away from nanometer, it's bad that they're 'forced' to move into Ångström.
I kinda like the sound of Intel 7 class manufacturing technology
Excellent summary.
I think calling it 4nm makes sense, since it is slightly more dense than most early 5nm nodes. This does all seem better...now, can they fix thier mobile and server chip nameing schemes please?
No, it doesn't make sense. The fundamental problem with calling these future process nodes by a "nanometer" measurement is that the transistors aren't all the same size! And when we start getting into Foveros packaging, tiles and all that, there will be /multiple/ process nodes on a /single/ chip!
It's the exact same thing we went through ~20 years ago when CPUs started including turbo boost and power efficiency modes. Before that, Intel, AMD, IBM, etc. were all including the megahertz in the product name, e.g. "Pentium 4 1.80 GHz", "Power PC G4 800" and so on. Everyone dropped these names in favour of product codes (e.g. "Intel Core 2 Duo E6600") because a single clock speed was no longer an accurate measure of performance.
@@warren_r It makes sense as just a label for comparison in that naming scheme. Of course using transistor type and density would make sense and be actually accurate.
I wish they had simply renamed it based on the density. Call it Intel 200 for 200 million transitors per mm^2
@@TauxWau I feel like they would need to estimate the density, since dram can be denser, so like 2:1 dram to logic density averaged for the "rating"
8:24 - beautiful pun my friend
I agree that it might be a good idea to drop the 'nm' from the naming in their nodes because they do not relate to structure width anymore. But why re-introducing the unit back in the angstrom era? Questions...
The 20A is interesting
Should probably wait for at least 2 pluses on that. That's when Intel recent nodes are at their best.
So 20A++. Which gets renamed to 16A.
@@stefangeorgeclaudiu Iterations will obviously always be better. :/ Does not mean initial releases will be bad. 14nm wasn't brilliant on first launch, but they fixed it up really quickly. The main thing that will matter is that it's better than what they had before. If it is, and yields aren't terrible, then it's worth using.
Once again Ian, excellent T shirt!
Thank you for the informative video.
One little problem I have with your depiction of Intel's plusses as half-nodes is that what Intel does with pluses is not the same as foundry half-nodes. For original 14nm Intel had a reported 44 MTr/mm2 density while for 14nm++ they had a reported 37 MTr/mm2 density. And Intel also stopped reporting chip density for 10nm. We don't really know the density of 10nm SuperFIN but since frequencies went up and power was increasing, I bet that 10nm+++ Enhanced SuperFIN has also degraded density.
The next best thing to compare Intel plusses would be performance variants from TSMC or Samsung, kind of like N7P is for N7.
The really interesting prospect of the naming change is that Intel now realize that they are not the current market leader, so they can no longer dictate how the industry names their processes.
And I'll also be interested in looking back at this in 4 years and see how far Intel has actually come of this roadmap. Given their track record to execute in recent years, and with the industry generally moving at a faster pace than Intel, I'll be extremely surprised if they manage it.
Intel hurt themselves a lot marketing wise by not following TSMC and samsung. Many people still think that these numbers mean something.
Agreed. I like this instead of the disclaimers that were always needed regarding the 'nm' values for each manufacturer.
Thanks for the info, Ian 👍
The problem is everyone knew the Intel node was superior for example 22nm vs 22nm. However when it's 10nm vs 7nm, Intel's now has no bias, even if they name 10nm 7 it's still going to be no better than the competition if the competition is on 7nm.
I really don't think this helps anyone, except for those that shouldn't be basing their decisions on processor nodes to begin with.
It would be nice to have an industry wide measuring stick but I don't think it will ever be that simple or really matter.
8:56 EUV do not use lenses, it is using mirrors only.
Yeah that's what I meant. It's all smoke and magic :)
Until now, nothing more than just a lot of marketing from Intel.
2022 here you got what you want
AMD much marketing, and burning cpus lol
Would you say that we have begun to see a shift in semiconductor development as a whole with companies like TSMC, Intel and AMD? It seems to me like packaging techniques are becoming a critical part of future performance improvements. Instead of the gains coming primarily from node shrinks and microarchitecture changes. Of course we will still see performance improvements due to those factors as well, but packaging seems like it will be playing a much bigger role.
Exciting stuff. Nothing like streamlining. I also plan to upgrade my PC in 2025 so I am excited what the options will be then.
I would've really preferred with some distinctive nomenclature since now you'll have i7 i5 and i3 processors made on Intel 7, Intel 4, Intel 3 ect nodes. Could've made the names somewhat more distinct from processor product lines.
They could of really ended the core branding if alder lake is truly going to match the leaked performance. Kill the core branding and get a new catchy name to market the dual architecture design and start back at 1 number wise
@@jsteezus The intel hybrid cores is something I feel like I'd like to get my mittens on, simply due to the unsymmetric processor cores, but they're probably going to be too expensive for a while for a toy.
@@nimeq I feel like you will benefit from waiting for the second generation of the hybrid design anyway since even if they have flawless execution on alder lake ( nothings ever perfect) theres going to be a lot of software that will take months and months to get updated to properly utilize the cores. Then there will be programs that use the cores, but dont use the right ones, or get expected performance but dont use the efficiency cores properly. Etc etc. I see second gen of this hybrid design being the one you wanna own if you want to really benefit from the promises heterogeneous core architectures on 1 chip can bring.
@@jsteezus I guess I should've stated that my interest in unsymmetric multiprocessing is as a software engineer. As a user it's a bit meh, since my current system is a amd ryzen 3900x desktop and a laptop with a amd ryzen 5800u. (and 3 corporate laptops of random specs)
Anybody confused over *that* is not the sort of person who is going to be paying attention to process nodes, and probably wouldn't even really understand what they are to begin with.
Thank You. :)
Glad it sounds like they're getting back on track. Hopefully no more issues with these future nodes with 10nm just being a fluke. Anyone know how foundries even begin to test something like 20A? 4yrs to go from FinFET to some drastically different transistor design, they have to know it will work? But how?
Key question: will this roadmap goose up Intel stock prices in the short term so that Intel senior executives can make themselves rich immediately off of more promises they never have to deliver on? I think we all know that Intel will probably not deliver on most of this roadmap in the longer-term (i.e. in reality) so the most important thing about it is will it fool Intel investors in buying more stock in the short term?
Intel's hired a lot of new people. Pat seems to be in for the long term, not the short term stock options.
@@TechTechPotato Let us hope so! It breaks my heart to see a great company like Intel lead to disaster. However, Intel’s leadership over the past four years has been abysmal and has provided little hope that it will get better soon. Also as the “mythical man month“ book reminds us, adding more people to a project in trouble often causes more problems than it solves.
A little bit offtopic, but can someone explain what happend to the whole electron migration thing? Just a few years back the consensus was that it would be basicly impossible to get lower then 5nm, somehow no one gives a crap about that. Did something change?
Can you quantify how much disadvantage Intel has from being x86 vs ARM?
Check my interview with Keller. He answers that
4%
I think there's something wrong with your mic. It seems to pick up breathing just after a sentence and makes it scratchy. Might be an audio filter you are using in Premiere or lack of.
So 14nm has been used right up to 11th gen, forcing them to cut bits off the i9 11900 so it would fit? And these nodes are coming in the future?
I wish they'd have departed from any physical units altogether and used completely new, incrementing process numbers, as is common in software version numbers.
But understandably having some comparison to already-known metrics, especially having their numbers being comparable to the competitors numbers is very important to them.
By the way, TSMC will just let Intel bypass them... just because... >XD
Not really, already it looks like TSMC is setting up a production facility at 2nm in 2024.
I'm reminded of when Microsoft had version numbers on apps that reflected the actual development cycle without concern for platform differences. So Excel on Windows had feature parity with the Mac version but the Mac version had a much higher version number because the first several versions were solely on Mac. This made for some annoying confusion for the marketing department, so it was declared one day that version numbers were now about features sets and two platforms that had feature parity would have the same version number regardless of disparity of how much longer one platform had been around compared to another.
What’s the min spec for cat chips?
Maybe they can work on the product naming next.
Soon every product will sound like a new high refresh monitor.
@@jsteezus NoooOoOooOoOooOoOoOooOoOoOo. please no 🥺
@@agenericaccount3935 I mean they are afraid to stop using current branding. This new alder lake if performance number is true would be the perfect time to end the core branding and start back over at 1 or something.
4:31 The unit has been changed from nanometres to marcommsmetres. Impressive that Intel then moves on to _deci_ marcommsmetres in the same press release.
Focusing on the now, does anyone know how does Intels new 7 nm (Prev. Enhanced SF) stacks against TSMC 5 nm? density wise
There's a table on AnandTech - about 200 vs 175 iirc
I believe what was previous 10 ESF (and what's coming with Alderlake) is Intel "7". Intel "4" is what their "7nm" is now called. That one is supposed to be roughly equivalent to TSMC's 5nm. Please correct me if I'm wrong.
TSMC node is going to have something close to 192 transitors/mm2
Intel’s is going to have something close to 200/mm2
Skipping vista, xp and 2000 and going straight from 7 to 4. Good move.
On the slide under Intel 4, it says "Full use of EUV lithography." Under Intel 3, it says "Increased EUV use." How can they increase use if they're already at full use?
At the current time, it's not worth the trouble to use EUV to litho any features other than for the finest gate structures in the bottom layers. You still finish everything else with DUV. "Increase" means use EUV for more layers.
So this 7 is 10 nm node size &
4 and 3 is 7 nm size of nodes.
Intel : When you can't shrink transistors size like competitors, change the name 🙃
well intels 10nm is the size of what TSMC 7nm so i would say they should have renamed it long ago since it causes confusion becuase for some reason a lot of people put that you should buy amd because it has 7nm and intel can barely do 10nm without knowing the full story
I had been looking forward to the day we switched from nm to Silicon atoms. 3 or 5 atoms per nm, depending on the crystal orientation. Also, transistors per square mm would have been a good way to define Intel’s manufacturing performance
If Intel indeed keeps their word with the naming scheme, I wonder how the other hardware reviewers would interpret it.
Thanks for the video, Ian!
I mean, they do delayed desktop 10nm for 5 years and just now they are producing more 10nm than 14nm. What could go wrong?
Make wafers does not mean make chips in spec.
10nm is 10nm. It is not necessarily indicative of what future processes will be. TSMC tripped up hard on 20nm and then got back on-track, for instance.
I like how you're wearing that Intel shirt for the video - I have one too :O
Finally, getting out of the loop of the plus's. Good job, Intel. I don't know about the die stacking cuz as what Dr. Ian said, the data and power comes together when travelling between the two dies, in which perhaps they need to decide which area does what process. It's interesting that we are going into new technologies.
Thank God! The past naming convention has been a huge marketing fiasco for Intel.
no it wasn't, the fiasco was their lack of progress.
The real fiasco will be a name going forward that is nothing but marketing BS, the waters are going to get muddy.
@@Commander_ZiN they were progressing all right just werent lowering the number for every BS change they did. how come they are equal with their 10nm in transistors per unit of area as TSMC's 7nm
@@bigpod because there transitors are shaped differently and therefore measured differently, so for it's size Intel was superior.
@@Commander_ZiN yes and no reality is at the end of the day only true messure we should care about how many transistors they can put in there
Thanks Ian! Great explanation of Intel's Jiggerypokerey.
Wouldn't have been better if they dropped the psedo feature size nomenclature and came up with an areal density vernacular instead ? Like 350 class, where the process has max transistor density of 350 million transistors/MM^2 ? That would be completely changing the game while still adhering to some industry convention
Excellent video, very informative, and interesting. Gives me new hope of Intel.
I need a chip made, I want to use 14nm+ Infinity -1... Okay, that was bad. But it really is about time Intel addressed this. And very glad about a road map, so lets hope they can execute the plans. :-)
3D chip stacking sounds great, but how are they going to cool eventual multichip stacking?
I believe the idea is to put the high powered cores at the top while less powerful cores or memory are at the bottom. This allow the hotter powerful cores to dissipate heat better
Also, presumably, the in silicon water cooling that has been being trialed
4 > 5 :) Got to love it.
i am dissapointed that they didnt start branding by average transistor density per square mm
would be intuitive and refreshing to go from 200m to 250m, very clear absolute numbers
Cheers
Holy hell, I'm learning so much in these videos... and yet, my eyes are fully transfixed on that reflective side of a CD hanging on the board in the background - trying to see what's going on in that reflection, why does it keep moving!?!
It's been hot in the UK, I have a fan on my legs that's blowing against and up the wall
Oh... that was a simple answer... :D
As long as they actually stick to this, it should help a lot in the future; but, in the present, I'm not so sure how much it helps. But, hey, gotta start somewhere.
I'm still on "believe it when I see it" with the 'new & improved' Gellsinger Intel, just like I have been with AMD/Radeon, but Pat does seem to be making very smart, deliberate changes to the way Intel is operating and should be operating into the future.
Things are definitely getting interesting as the [high performance] industry transitions to EUV, 3D construction becomes mass production viable, local memory is multiplying in size, of course the new pressure that Apple has put on the rest of the industry, etc., interesting times!
While I'm here I'd like to say you were mentioned on tech linked!
So they go to a non-SI unit from nm instead of going to pm.
I get that they can not go far below nm still using angstroms is not a great idea hope other will not copy this.
I think samsung was the first to use anm for some memory tech a short while back.
With some luck, 20A might not also be what those chips pull from the 12V rail
is that a Corsair 760T case on the bottom right of the screen?
It is
@@TechTechPotato Very nice, on the same topic. What did you think about Hamilton's move on Max at the British GP?
What Nvidia gpu is that behind Ian?
ruclips.net/video/M7kB0fGom1g/видео.html
i see that sub count Easter egg, wink wink
congrats Ian you deserve more than 50k
14nm was late, 10nm was late, Intel 4 (7nm) is late so I will believe they can execute when they actually deliver.
I wonder if processors will get more fragile as the process goes smaller and smaller? By this I mean a chip would only work for a year or two before breaking.
Intel should let Dr. Kelleher do all the presentations. This roadmap gives me hope; coming from an exclusively-AMD user.
Personally I find it really sad that Intel had to stoop to TSMC's and Samsung's level. Intel's numbers were at least honest and proper for what the transistor density was.
Yeah I too am very sad. However so many people were confused but the current situation, probably younger people.
I don't think this was the way, all they needed to do was make some progress.
Can I run my research reactor on Linode and cross my fingers I don’t get a fiber cut? Maybe not! Yes, Linode are good guys!
I never really understood the physics that make smaller more power efficient. It's not resistance so I guess the key is lowering capacitance?
Think of it this way, walk from one side of the room to the other, then to the centre of the room , you just used 1/2 of the energy to get to the centre then walking across the entire room , less distance = you need less energy to move electrons across the chip .
@@lasarith2 I don't think the distance electrons have to travel makes much difference. Unless it's a very long distance.
@@oraz. it’s been a while since I looked into this , but the smaller distance means the transistors can switch on/off faster, meaning they use less energy then a larger transistor, on average TSMC says by about 30% reduction in power from 10nm to 7nm to 5nm etc, the smaller the transistor the less energy is needed to be on/off .
The old + made intel look stagnant changing it up makes them look more competent.
Does he have his videos dubbed? Sound doesn’t seem to be current with picture! Oh well, I will keep watching. Lol
With all the naming mumbo-jumbo, will we even notice if there will be a real transition from a 5nm to 3nm node, performance-wise, or will we get a myriad of process node names across 5 years instead just to hide the fact it's again not going as planned like in the couple years after 2012?
What is the significance of Intel 3 having “increased intrinsic drive current”?
So Intel are 4 packaging generations away from what AMD (with TSMC) are going to bring out later this year???
Exactly
Didn't TSMC have like N7P and N7+ nodes?
12:50 my argument is "no"
good argument
Well - lets just hope for all of us that Intel can execute this time. 10nm took 5 years longer than they anticipated, that happening a second time would really start to hurt them.
Start? This 5 year delay is about to eviscerate their balance sheet. A second one could result in bankruptcy. You have to understand these things are offset by a few years, although they’ve been falling behind for years now it’s only recently that it started to reflect in their finances. The only thing that has kept them in the black at this point is the fact that their production capacity was much higher than their competitors. That is swiftly coming to an end however.
@@samuel5916 2020 was their best FY yet iirc, they might have lost business but far from on the brink of bankruptcy.
@@axiom1650 You didn’t read what I said. I said that a second 5-year delay and falling behind other foundries could result in bankruptcy. This one is recoverable but it gave a golden opportunity for their competitors to steal market-share and that is starting to ramp up faster now that other companies are ramping their wafer supplies. By the end of this year AMD will be TSMC’s second largest customer by volume (after Apple) and the largest on 7nm. Nvidia switching to Samsung gave them access to enormous supply with fewer competitors to compete with wafers for and it’s injecting a lot of cash and confidence into Samsung’s foundry business which will directly fund their efforts to be more competitive on leading edge nodes.
Intel shot themselves in the dick and squandered their lead but there’s no reason they can’t get back on track in the next three years. In the meantime, their competitors (especially AMD) will have a field day stealing marketshare and Intel’s main weapon will be capacity which they can use to compete with lower prices to keep revenue up. However, that will take a heavy toll on their fat profit margins which will piss off investors. In three years time AMD and Nvidia could be very close to Intel’s annual revenue with higher profit margins. So once everything stabilizes the playing field will be leveled and the competition fierce, which is good for consumers.
@@samuel5916 "This 5 year delay is about to eviscerate their balance sheet."
So far they are doing better than ever, just the growth was not as high as they would have liked, but not only are they selling more 14nm than AMD is selling 7nm, they are selling more 10nm as well....
"You have to understand these things are offset by a few years"
Yes - i do, your point is?
"I said that a second 5-year delay and falling behind other foundries could result in bankruptcy."
Yeah, and that assumption is just wrong or TSMC would have died long ago.
"and Intel’s main weapon will be capacity"
the capacity of 10nm - were processes like Lakefield have shown that they are also more efficient than anything else on the marked right now.
"However, that will take a heavy toll on their fat profit margins which will piss off investors."
No, as we can see - not gonna happen. Specially now that AMD has also increased their prices to gain higher margins, making it far easier for Intel as well.
"In three years time AMD and Nvidia could be very close to Intel’s annual revenue"
Ahahahahahaha - No. Even if AMD and Nvidia grew 50% each year now (yeah, as if that gonna happen) they would together not even be half of Intel...... You really should look at the actual numbers before writing.
@@ABaumstumpf I have, I regularly invest in all three companies and have made quite a bit of money doing so. How? Because I understand how this industry works and I follow the patterns.
I want a 2nm tsmc 6 arm 98c cores enhanced photon computing in the GPU for inferencing. This should look cool at 720p only using about 18 watts. That's what I want a mid decade low watt gaming system.
I want to buy a new PC by the end of 2022 buy it seems I will have to wait a little more. I am actually really excited for Intel's GPU more than their CPUs. Wonder what the future of GPUs will be with these new nodes. Hopefully intel will use their cutting edge nodes for GPUs and not have them be second though since AMD and Nvidia always use nodes that are 1 or 2 years behind the CPUs
Why did they ditch the picometer unit and went straight to angstrom?
1Å=100pm. Do you figure Intel 2000p is a better name?
@@LA-MJ 😭 true
IAN "TALK IS CHEAP" CUTRESS
Loved hearing you on the official Intel video
Okay, so when are we going to be breaking though the 5ghz bottleneck? That was why it was exciting to have proccessor shrinkage after all. Or are we going to get a hundred cores that we don't need to use while keeping under 5ghz?
I think the names are missing something. Like with 20A, 18A, maybe Intel should adopt 7N, 4N, 3N for these nodes. "Intel 7" just seems... empty?
I am just adding to the chorus but I was disappointed that they didn't just try to name it based on density and increment UP instead of down. Intel is big enough they could set the trend here.
How long does it take for people to realize that a node is NOT a point, but a curve? A curve between perf to density, power to perf, etc. NO ONE LABELS A CURVE BY ITS RIGHTMOST POINT (e.g. max density)
It is my humble opinion that Pat Gelsinger is the best person to get Intel back on top of its game again.
3:58 Samsung 7nm uses EUV and 10/8nm doesn't. 5nm is what 7 should've been and 6 is a kinda fix for broken 7nm.
How do you get to the conclusion that these processes are all similar? It's clearly two different ones. With 5 different names between them
Similar PDK and design rules but using EUV over DUV to reduce steps. That's not really a change if the design rules are roughly the same and the features are as well.
Starttrek wiki for angstroms, is Intel working on teleportation devices?
If only there was a regalutory body, forcing companies to name their nodes depending on actual transistor size
So, if you love consistency, then you must hate turbo boost?
The second Ian posts a new video my day is made! You are making a lot of us regular non doctors of computer stuff a lot smarter every video you post.