- Видео 96
- Просмотров 109 313
We_LSI
Добавлен 10 авг 2023
Hello VLSI enthusiasts...
Welcome to my We_LSI ! This channel is here to help you learn Verilog, SystemVerilog, and UVM.
You can find verilog and system verilog videos here. Planned to cover complete system verilog concepts and also some of the protocol videos. These videos are mainly for freshers and those who are new to system verilog. I might have missed few points while explaining but please make sure to clear your doubts at that instant only.
"It is what we know already that often prevents us from learning" ^_^
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“You don't need more time, you need more focus”
Welcome to my We_LSI ! This channel is here to help you learn Verilog, SystemVerilog, and UVM.
You can find verilog and system verilog videos here. Planned to cover complete system verilog concepts and also some of the protocol videos. These videos are mainly for freshers and those who are new to system verilog. I might have missed few points while explaining but please make sure to clear your doubts at that instant only.
"It is what we know already that often prevents us from learning" ^_^
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“You don't need more time, you need more focus”
Program Block PART - 3 in Systemverilog #systemverilog #vlsi #verification #tutorial #semiconductor
0:17 :Introduction
7:31 :Key points of program block
12:08 :Similarities between module and program block
13:08 :Differences between module and program block
7:31 :Key points of program block
12:08 :Similarities between module and program block
13:08 :Differences between module and program block
Просмотров: 204
Видео
Program Block PART - 1 in Systemverilog #systemverilog #vlsi #verification #tutorial #semiconductor
Просмотров 26221 день назад
0:17 :Introduction 7:31 :Key points of program block 12:08 :Similarities between module and program block 13:08 :Differences between module and program block
Race condition and Event scheduling in #systemverilog #vlsi #verification #tutorial #semiconductor
Просмотров 634Месяц назад
0:12 :Introduction 4:28 :Race condition examples 9:05 :Guidelines for avoiding race condition 10:27 :System verilog event regions
Examples for Constraint #systemverilog | PART-2 |Constraints Q&A #vlsi #learn #coding #semiconductor
Просмотров 1,4 тыс.4 месяца назад
Examples for Constraint #systemverilog | PART-2 |Constraints Q&A #vlsi #learn #coding #semiconductor
Examples for Constraint #systemverilog | PART-1 |Constraints Q&A #vlsi #learn #coding #semiconductor
Просмотров 1,3 тыс.4 месяца назад
Examples for Constraint #systemverilog | PART-1 |Constraints Q&A #vlsi #learn #coding #semiconductor
Constraints in #systemverilog | PART-8 | rand_mode and constraint_mode in constraints #vlsi #learn
Просмотров 6574 месяца назад
Constraints in #systemverilog | PART-8 | rand_mode and constraint_mode in constraints #vlsi #learn
Constraints in #systemverilog | PART-7 | Bidirectional and Solve-before constraints #vlsi #learn
Просмотров 8924 месяца назад
Constraints in #systemverilog | PART-7 | Bidirectional and Solve-before constraints #vlsi #learn
Constraints in #systemverilog | PART-6 | implication operator and if-else construct in constraint
Просмотров 8145 месяцев назад
Constraints in #systemverilog | PART-6 | implication operator and if-else construct in constraint
Randomization and Constraints in #systemverilog | PART-5 | with and soft keyword in constraint #vlsi
Просмотров 1 тыс.5 месяцев назад
Randomization and Constraints in #systemverilog | PART-5 | with and soft keyword in constraint #vlsi
Randomization and Constraints in #systemverilog | PART-4 | dist keyword in constraint #vlsi
Просмотров 1,2 тыс.5 месяцев назад
Randomization and Constraints in #systemverilog | PART-4 | dist keyword in constraint #vlsi
Randomization and Constraints in #systemverilog | PART-3 | inside keyword in constraint #vlsi
Просмотров 1,1 тыс.5 месяцев назад
Randomization and Constraints in #systemverilog | PART-3 | inside keyword in constraint #vlsi
Randomization and Constraints in #systemverilog | PART-2 | inside keyword in constraint #vlsi
Просмотров 1,5 тыс.5 месяцев назад
Randomization and Constraints in #systemverilog | PART-2 | inside keyword in constraint #vlsi
Randomization in #systemverilog | PART-1 | Introduction to #randomization| #oop #vlsi #verification
Просмотров 2 тыс.6 месяцев назад
Randomization in #systemverilog | PART-1 | Introduction to #randomization| #oop #vlsi #verification
Scope resolution operator in #systemverilog | Introduction & Examples| #verification #semiconductor
Просмотров 1,1 тыс.6 месяцев назад
Scope resolution operator in #systemverilog | Introduction & Examples| #verification #semiconductor
Virtual class in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor
Просмотров 1,3 тыс.6 месяцев назад
Virtual class in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor
Virtual keyword in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor
Просмотров 1,4 тыс.7 месяцев назад
Virtual keyword in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor
Mailbox in System verilog | Part 2 | Examples| #systemverilog #vlsi
Просмотров 1,3 тыс.7 месяцев назад
Mailbox in System verilog | Part 2 | Examples| #systemverilog #vlsi
Mailbox in System verilog | Part 1 | Introduction | #systemverilog #vlsi
Просмотров 1,8 тыс.7 месяцев назад
Mailbox in System verilog | Part 1 | Introduction | #systemverilog #vlsi
super keyword in #systemverilog |Introduction & Examples|#vlsi #verification #verilog #semiconductor
Просмотров 1,3 тыс.7 месяцев назад
super keyword in #systemverilog |Introduction & Examples|#vlsi #verification #verilog #semiconductor
this keyword in #systemverilog | Introduction & Examples|#vlsi #verification #verilog #semiconductor
Просмотров 1,3 тыс.7 месяцев назад
this keyword in #systemverilog | Introduction & Examples|#vlsi #verification #verilog #semiconductor
Inheritance in #systemverilog | PART-2 | Examples for #inheritance | #oop #vlsi #verification #dv
Просмотров 1,2 тыс.7 месяцев назад
Inheritance in #systemverilog | PART-2 | Examples for #inheritance | #oop #vlsi #verification #dv
Inheritance in #systemverilog | PART-1 | Introduction to #inheritance | #oop #vlsi #verification
Просмотров 1,5 тыс.7 месяцев назад
Inheritance in #systemverilog | PART-1 | Introduction to #inheritance | #oop #vlsi #verification
Static class members in System verilog | PART-1 | Static properties & methods in #systemverilog
Просмотров 1,9 тыс.7 месяцев назад
Static class members in System verilog | PART-1 | Static properties & methods in #systemverilog
Classes in System verilog | PART-2 Examples |#classes in #systemverilog | OOPs in system verilog
Просмотров 2,2 тыс.7 месяцев назад
Classes in System verilog | PART-2 Examples |#classes in #systemverilog | OOPs in system verilog
Classes in System verilog | PART-1 Introduction |#classes in #systemverilog | OOPs in system verilog
Просмотров 5 тыс.7 месяцев назад
Classes in System verilog | PART-1 Introduction |#classes in #systemverilog | OOPs in system verilog
Semaphores in System verilog | Part 1 | Introduction | #systemverilog #vlsi
Просмотров 1,7 тыс.8 месяцев назад
Semaphores in System verilog | Part 1 | Introduction | #systemverilog #vlsi
$unit and $root in System verilog | Part 2 | Introduction | #systemverilog |
Просмотров 4428 месяцев назад
$unit and $root in System verilog | Part 2 | Introduction | #systemverilog |
$unit and $root in System verilog | Part 1 | Introduction | #systemverilog |
Просмотров 5208 месяцев назад
$unit and $root in System verilog | Part 1 | Introduction | #systemverilog |
Threads/Processes in System verilog | fork join constructs & process control | #systemverilog |
Просмотров 1,7 тыс.8 месяцев назад
Threads/Processes in System verilog | fork join constructs & process control | #systemverilog |
Packages in System verilog | Part 2 | Examples for packages | #systemverilog |
Просмотров 4378 месяцев назад
Packages in System verilog | Part 2 | Examples for packages | #systemverilog |
Good question 😊
Thank you
Veryy very helpful madam.....thank a lot......🥰
Thank you:)
will you start UVM!!
@@PrashanthsVlog Yes but once i complete coverages n assertions
Yes please, we will wait for the most, really great video because you are not only explaining theoretically but also executing sv codes practically for students great.... 💯 Waiting for UVM...
@@PrashanthsVlog Sure .Thank u
Mam can you explain vector[3:0] and array[3:0]
Watch PART 2 I have explained the difference here: ruclips.net/video/oup0gqzipBw/видео.htmlsi=KZvkOYvJKlIN91GA
Is notes provided
No. For constraints and interview questions notes are available. for more details: linkedin.com/in/susheelapatagar
Can we also use int instead of bit data types
Yes we can.
thank for the clear expalination mam and please explain the all topics in system verilog and this is request for all member is could you pls explain the how to write the testbench in system verilog plss mam we need ur video it will be more helpful us mam 🙂🙂
Thank you. and Yeah will do everything one by one
Mam Make acces for shallow copy nd deep copy video...
Sorry few videos are made members-only. So join the channel and get access to members-only videos.
Nice explaination mam.Can we use a logic data type in randomization,for ex. "rand logic abc" in class definition?
Yes we can use reg,logic. But randomization does not support 4 state values(x/z are not randomized only 0/1 is allowed).
@@susheelapatagar Thank you mam🙏
Please do uvm mam😊
Yes I will but let me finish sv first
Hi, I have a question about using the `this keyword in static functions. I understand that static functions can't use the `this keyword because they can't access class properties, which are automatic by default. However, even when I explicitly declare class properties as static, I'm still getting an error saying that the `this keyword is illegal to use in static functions. Could you please clarify why this is happening?
A static method means that only one copy of the method exists, and it belongs to the class itself, not to any particular instance of the class. The 'this' keyword refers to the current instance of a class, which is why it cannot be used in a static method. Static methods can only access static variables, which are shared across all instances of the class. Since 'this' implies a reference to a specific instance, using it in a static context would be contradictory, as static methods and variables are not tied to any single instance but to the class as a whole.
best explained
@@Muskaanhayat Thank you 🎉💜
expect more vdeos please
👍
Good content and presentation as well.
Thank you
plz continue making videos ,these are useful for many
Sure!
Mam protocols
Yeah👍
Reply me mam And start UVM as well plz
UVM takes time.
Can u start assertions a d coverage
Yeah
superb
@@reshmahayat2132 Thank you ✨
Could you please make a video on semaphore with an examples.
@@KiranKumar-tp3ri I have already uploaded it. But it's a 'members only' video Link: ruclips.net/video/7aqaW1qJQQs/видео.htmlsi=oGIw9x9F7anOEsY6
@@susheelapatagar okay, thank you
Thank you so much mam. Very well explained.
Thank you
Nice. I like it. Please do it everyday. I have subscribed it so i get updates
@@supreethathreyas4577 Thanks. I will upload as much as possible
Thank you ❤
@@rekhanaik8262 You're welcome ✨
Mam please explain about coverage and its types thank you
Yeah I will 👍
Hi Mam , Uvm tutorial from begining
Yeah but before that let me finish SV.
Nice explanation mam, plz provide code in description mam , thank you
Its already there in description please check it once.
Great 👍
Thank you ✨
Please continue this series on verilog, I'm an rtl intern
@@MSQ819 sure 👍
Great explanation, thanks
@@MSQ819 You're welcome ✨
Callbacks (post_randomize) 👍
Yes
🎉
Hi mam Mam can u do video for system verilog interface and modports with suitable example
Okay.
Mam tell with an example for constraints
ruclips.net/video/0ILdGOI25cI/видео.htmlsi=OiTMlJa-fvcbhedO
Tell with an example plz
ruclips.net/video/2wv8r04yEgM/видео.htmlsi=FTFu6aAD-wcWlty4
You are amazing 👌👌
Thanks😁🥳
Wow, amazing 👌👌👌
Thank you.
mam explain how to access the automatic ,,, increment_static.count_b
Generally, we can't access local variables outside their function or task directly. However, if the variable is static, as explained in the video, it can be accessed. For automatic variables, hierarchical references are not allowed. To work around this, you can declare a variable in the module (outside the function/task) and assign the local automatic variable to this module-level variable inside the function/task. This way, when you need to print or use the variable outside the function/task, you can simply use that module variable.
Thankyou mam
Upload the example program for fork join
@@ec-213narendrareddy5 already uploaded(Members only video) ruclips.net/video/iVZz9cXNDGA/видео.htmlsi=2SNSC7jySD8ov9RH
Can you generate 2 multiplication table
Sure. Here you go: (Change N value to get any table) `define N 2 class packet; rand bit[31:0]a; int b=1; constraint c1{a ==`N * b;} function void post_randomize(); $display("%0d * %0d = %0d",`N,b,a); b++; //incrementing b value endfunction endclass module pattern; packet p; initial begin p=new(); repeat(10)begin p.randomize(); end end endmodule
GOOD EXPLANATION 👏👏👏
@@mark_RRR12 Thank you .♡
Thanks!
@@mark_RRR12 You're welcome✨ and Thankiew :) You are the first subscriber to send Super thanks.🤝
Best explanation with relevant example ❤️👏
@@ShwetaSPujeri Thank you ❣️
After a long time new video
@@rohitshet2079 yeah.🙋
I watched all of your system verilog ------very very helpful mam
@@vishalgowtham896 I am happy to hear that :)
What if it is not time consuming? In order to that we can call directly??
@@uditgohil7547No. tasks cannot be enabled inside the function.(But synopsys and questa simulator allows it with warning)
usually the tasks are programmed not to consume time. But its not compulsory. As shown in the shorts
Excellent explanation madam
@@Srikarthik Thank you:)
Concept helps a lot! Godgifted madam 🙌
It's working for the pre_randomize function as well, why ?
its because of randomization.if not zero, other value would have been printed right, so in this case 0 only printed thats it. It is also tool dependedent. try with aldec/questa it wont work for pre_randomization.(only in synopsys u will get 0.)
We can do with non_blocking statements. But It's another way to swap Good 👍
Yes.