VLSI academia
VLSI academia
  • Видео 16
  • Просмотров 26 353
Modports
What are Modports
How to Select Modport Definition in Modules
What are Generic Interface Ports
#vlsi #verilog #interview #digital #logic
VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Electronics. We believe it's the era of electronics and VLSI in shaping the world into a better one
Come join VLSI Academia and contribute to the building of new safe, developed and prosperous world
Просмотров: 1 041

Видео

UVM Phases14:52UVM Phases
UVM Phases
Просмотров 1,2 тыс.Год назад
Learn about what are UVM Phases ? Why do we need phasing in UVM ? #vlsi #verilog #interview #digital #logic #verification #digitaldesign #rtl #interviewquestions #uvm #systemverilog VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Electronics. We believe it's the era of electronics and VLSI in shaping the world int...
Setup & Hold Analysis | Fix Setup and Hold Analysis48:39Setup & Hold Analysis | Fix Setup and Hold Analysis
Setup & Hold Analysis | Fix Setup and Hold Analysis
Просмотров 1,7 тыс.Год назад
This video tells about the setup and hold analysis, clocked storage element(Flipflop and Latches). It also tells about the setup and hold slack and it calculation. It discuss about the possible cause of setup and hold violation and how we can fix setup and hold violation #vlsi #verilog #interview #digital #logic #sta #statictiminganalysis #timing #digitaldesign VLSI Academia is a VLSI community...
Event Regions in Verilog and Race Condition18:35Event Regions in Verilog and Race Condition
Event Regions in Verilog and Race Condition
Просмотров 4,3 тыс.Год назад
What are Event Regions in Verilog? How scheduling of events happen in Verilog What is Race Condition in Verilog and how we can avoid it #vlsi #verilog #interview #digital #logic #verification #digitaldesign #rtl #interviewquestions VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Electronics. We believe it's the er...
Static timing Analysis in Design Flow21:37Static timing Analysis in Design Flow
Static timing Analysis in Design Flow
Просмотров 1,2 тыс.Год назад
#vlsi #verilog #interview #digital #logic #sta #statictiminganalysis VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Electronics. We believe it's the era of electronics and VLSI in shaping the world into a better one Come join VLSI Academia and contribute to the building of new safe, developed and prosperous world
SV Verification Constructs | Final Block | Fork Join | join_any | join none | disable and wait fork16:46SV Verification Constructs | Final Block | Fork Join | join_any | join none | disable and wait fork
SV Verification Constructs | Final Block | Fork Join | join_any | join none | disable and wait fork
Просмотров 1,1 тыс.Год назад
Verification Constructs added in SV : Final Block Fork Join Enhancements of fork join - join_any and join_none disable and wait fork #vlsi #verilog #interview #digital #logic VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Electronics. We believe it's the era of electronics and VLSI in shaping the world into a bet...
Interfaces in System Verilog17:06Interfaces in System Verilog
Interfaces in System Verilog
Просмотров 2 тыс.Год назад
What is an interface in System Verilog. Why do we need interfaces How to access Interface Signals External ports in Interface #vlsi #verilog #interview #digital #logic VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Electronics. We believe it's the era of electronics and VLSI in shaping the world into a better one...
Design gates (NOT/ OR/ AND/ XOR/ XNOR/ Full adder) using mux16:36Design gates (NOT/ OR/ AND/ XOR/ XNOR/ Full adder) using mux
Design gates (NOT/ OR/ AND/ XOR/ XNOR/ Full adder) using mux
Просмотров 1,3 тыс.Год назад
Design/ Implement Not gate using Mux Design/ Implement Buffer gate using Mux Design/ Implement AND gate using Mux Design/ Implement OR gate using Mux Design/ Implement XOR gate using Mux Design/ Implement XNOR gate using Mux Design/ Implement Full adder using Mux #vlsi #verilog #interview #digital #logic VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a co...
Time literal and timescale in System Verilog | Timeunit | Timeprecision7:16Time literal and timescale in System Verilog | Timeunit | Timeprecision
Time literal and timescale in System Verilog | Timeunit | Timeprecision
Просмотров 2 тыс.Год назад
Introduction of Time literal and timescale compiler directive. System Verilog added features to define timeunit and timeprecision for specific module in the hierarchy VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Electronics. We believe it's the era of electronics and VLSI in shaping the world into a better one ...
User defined data type in System Verilog | Enumerated Data Types | typedef10:41User defined data type in System Verilog | Enumerated Data Types | typedef
User defined data type in System Verilog | Enumerated Data Types | typedef
Просмотров 1,7 тыс.Год назад
System Verilog for Verification User defined data types in System Verilog What is enumerated data types in System Verilog ? Advantages of enumerated data types What is typedef in System Verilog? How to use typedef and it's advantages #vlsi #verilog #verification #systemverilog #OOPs VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explo...
What is Static timing analysis | Why it is important9:21What is Static timing analysis | Why it is important
What is Static timing analysis | Why it is important
Просмотров 1,2 тыс.Год назад
Here in this Video I have discussed about the motive of STA, its definition and why it is important #vlsi #verilog #interview #digital #logic #sta #statictiminganalysis #timing #digitaldesign VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Electronics. We believe it's the era of electronics and VLSI in shaping the...
Design gates (NOT/ OR / AND / XOR / XNOR/ Majority) using NAND gate14:08Design gates (NOT/ OR / AND / XOR / XNOR/ Majority) using NAND gate
Design gates (NOT/ OR / AND / XOR / XNOR/ Majority) using NAND gate
Просмотров 1,3 тыс.Год назад
Design/ Implement Not gate using NAND gate Design/ Implement Buffer gate using NAND gate Design/ Implement AND gate using NAND gate Design/ Implement OR gate using NAND gate Design/ Implement XOR gate using NAND gate Design/ Implement XNOR gate using NAND gate Design/ Implement Majority gate using NAND gate #vlsi #verilog #interview #digital #logic VLSI Academia is a VLSI community to help and ...
Static vs Dynamic Timing Analysis | Basic of Static Timing Analysis19:50Static vs Dynamic Timing Analysis | Basic of Static Timing Analysis
Static vs Dynamic Timing Analysis | Basic of Static Timing Analysis
Просмотров 2,2 тыс.Год назад
This video will explain basic of timing analaysis, and moving forward it will explain the difference between Static and Dynamic Timing Analysis #vlsi #verilog #static_timing_analysis #STA #dynamictiming #sta VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Electronics. We believe it's the era of electronics and VLS...
Classes in System Verilog - Part II | SV for Verification and OOPs concept10:14Classes in System Verilog - Part II | SV for Verification and OOPs concept
Classes in System Verilog - Part II | SV for Verification and OOPs concept
Просмотров 1,3 тыс.Год назад
System Verilog for Verification What is a Class Constructor ? How to make configurable class constructor How to access class properties and methods using dot operator How automatic deallocation of memory works #vlsi #verilog #verification #systemverilog #OOPs #class VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of ...
Classes in System Verilog - Part I | SV for Verification and OOPs concept12:10Classes in System Verilog - Part I | SV for Verification and OOPs concept
Classes in System Verilog - Part I | SV for Verification and OOPs concept
Просмотров 1,7 тыс.Год назад
System Verilog for Verification What is a class in System Verilog? How to Create Class? Why do we need class? What are the advantages of class as compared to traditional method? What is Class Handles and Objects? #vlsi #verilog #verification #systemverilog #OOPs VLSI Academia is a VLSI community to help and connect top VLSI aspirants and give them a common platform to explore the domain of Elec...
Basics of classes - Introduction4:59Basics of classes - Introduction
Basics of classes - Introduction
Просмотров 1 тыс.Год назад
Basics of classes - Introduction

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